| Message ID | 20220620115549.1529597-1-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output | expand |
On 6/20/22 13:55, Anup Patel wrote: > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> Looks good to me. I only tested on QEMU where all values default to 0. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > arch/riscv/kernel/cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..c037b8691bbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -3,10 +3,13 @@ > * Copyright (C) 2012 Regents of the University of California > */ > > +#include <linux/cpu.h> > #include <linux/init.h> > #include <linux/seq_file.h> > #include <linux/of.h> > +#include <asm/csr.h> > #include <asm/hwcap.h> > +#include <asm/sbi.h> > #include <asm/smp.h> > #include <asm/pgtable.h> > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node *node) > } > > #ifdef CONFIG_PROC_FS > + > +struct riscv_cpuinfo { > + unsigned long mvendorid; > + unsigned long marchid; > + unsigned long mimpid; > +}; > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > + > +static int riscv_cpuinfo_starting(unsigned int cpu) > +{ > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > + > +#if defined(CONFIG_RISCV_SBI) > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > +#elif defined(CONFIG_RISCV_M_MODE) > + ci->mvendorid = csr_read(CSR_MVENDORID); > + ci->marchid = csr_read(CSR_MARCHID); > + ci->mimpid = csr_read(CSR_MIMPID); > +#else > + ci->mvendorid = 0; > + ci->marchid = 0; > + ci->mimpid = 0; > +#endif > + > + return 0; > +} > + > +static int __init riscv_cpuinfo_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", > + riscv_cpuinfo_starting, NULL); > + if (ret < 0) { > + pr_err("cpuinfo: failed to register hotplug callbacks.\n"); > + return ret; > + } > + > + return 0; > +} > +device_initcall(riscv_cpuinfo_init); > + > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > { \ > .uprop = #UPROP, \ > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); > const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > seq_puts(m, "\n"); > of_node_put(node); >
Hey Anup, Tested it & got back the (sadly boring) 0s that are set in my hardware. Two comments below. Thanks, Conor. On 20/06/2022 12:55, Anup Patel wrote: > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/kernel/cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..c037b8691bbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -3,10 +3,13 @@ > * Copyright (C) 2012 Regents of the University of California > */ > > +#include <linux/cpu.h> > #include <linux/init.h> > #include <linux/seq_file.h> > #include <linux/of.h> > +#include <asm/csr.h> > #include <asm/hwcap.h> > +#include <asm/sbi.h> > #include <asm/smp.h> > #include <asm/pgtable.h> > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node *node) > } > > #ifdef CONFIG_PROC_FS > + > +struct riscv_cpuinfo { > + unsigned long mvendorid; > + unsigned long marchid; > + unsigned long mimpid; > +}; > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > + > +static int riscv_cpuinfo_starting(unsigned int cpu) > +{ > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > + > +#if defined(CONFIG_RISCV_SBI) This should be #if IS_ENABLED(CONFIG_RISCV_SBI) to match the other users > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > +#elif defined(CONFIG_RISCV_M_MODE) Ditto > + ci->mvendorid = csr_read(CSR_MVENDORID); > + ci->marchid = csr_read(CSR_MARCHID); > + ci->mimpid = csr_read(CSR_MIMPID); > +#else > + ci->mvendorid = 0; > + ci->marchid = 0; > + ci->mimpid = 0; > +#endif > + > + return 0; > +} > + > +static int __init riscv_cpuinfo_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", > + riscv_cpuinfo_starting, NULL); > + if (ret < 0) { > + pr_err("cpuinfo: failed to register hotplug callbacks.\n"); > + return ret; > + } > + > + return 0; > +} > +device_initcall(riscv_cpuinfo_init); > + > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > { \ > .uprop = #UPROP, \ > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); > const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > seq_puts(m, "\n"); > of_node_put(node); >
Hello Anup! On Mon, 20 Jun 2022 17:25:49 +0530 Anup Patel <apatel@ventanamicro.com> wrote: > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. Tested on Sifive Unmatched: localhost / # cat /proc/cpuinfo processor : 0 hart : 4 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 1 hart : 1 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 2 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 3 hart : 3 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 mvendorid, marchid values match the register description in u74 manual. mimpid seems to be ok, through i can't find exact in U74/Unmatched docs. Tested-by: Nikita Shubin <n.shubin@yadro.com> > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/kernel/cpu.c | 51 > +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 > insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..c037b8691bbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -3,10 +3,13 @@ > * Copyright (C) 2012 Regents of the University of California > */ > > +#include <linux/cpu.h> > #include <linux/init.h> > #include <linux/seq_file.h> > #include <linux/of.h> > +#include <asm/csr.h> > #include <asm/hwcap.h> > +#include <asm/sbi.h> > #include <asm/smp.h> > #include <asm/pgtable.h> > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node > *node) } > > #ifdef CONFIG_PROC_FS > + > +struct riscv_cpuinfo { > + unsigned long mvendorid; > + unsigned long marchid; > + unsigned long mimpid; > +}; > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > + > +static int riscv_cpuinfo_starting(unsigned int cpu) > +{ > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > + > +#if defined(CONFIG_RISCV_SBI) > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > +#elif defined(CONFIG_RISCV_M_MODE) > + ci->mvendorid = csr_read(CSR_MVENDORID); > + ci->marchid = csr_read(CSR_MARCHID); > + ci->mimpid = csr_read(CSR_MIMPID); > +#else > + ci->mvendorid = 0; > + ci->marchid = 0; > + ci->mimpid = 0; > +#endif > + > + return 0; > +} > + > +static int __init riscv_cpuinfo_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > "riscv/cpuinfo:starting", > + riscv_cpuinfo_starting, NULL); > + if (ret < 0) { > + pr_err("cpuinfo: failed to register hotplug > callbacks.\n"); > + return ret; > + } > + > + return 0; > +} > +device_initcall(riscv_cpuinfo_init); > + > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > { \ > .uprop = #UPROP, \ > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, > cpu_id); const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > seq_puts(m, "\n"); > of_node_put(node); >
On Tue, Jun 21, 2022 at 10:53 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote: > > Hello Anup! > > On Mon, 20 Jun 2022 17:25:49 +0530 > Anup Patel <apatel@ventanamicro.com> wrote: > > > Identifying the underlying RISC-V implementation can be important > > for some of the user space applications. For example, the perf tool > > uses arch specific CPU implementation id (i.e. CPUID) to select a > > JSON file describing custom perf events on a CPU. > > > > Currently, there is no way to identify RISC-V implementation so we > > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > > Tested on Sifive Unmatched: > > localhost / # cat /proc/cpuinfo > processor : 0 > hart : 4 > isa : rv64imafdc > mmu : sv39 > uarch : sifive,bullet0 > mvendorid : 0x489 > marchid : 0x8000000000000007 > mimpid : 0x20181004 > > processor : 1 > hart : 1 > isa : rv64imafdc > mmu : sv39 > uarch : sifive,bullet0 > mvendorid : 0x489 > marchid : 0x8000000000000007 > mimpid : 0x20181004 > > processor : 2 > hart : 2 > isa : rv64imafdc > mmu : sv39 > uarch : sifive,bullet0 > mvendorid : 0x489 > marchid : 0x8000000000000007 > mimpid : 0x20181004 > > processor : 3 > hart : 3 > isa : rv64imafdc > mmu : sv39 > uarch : sifive,bullet0 > mvendorid : 0x489 > marchid : 0x8000000000000007 > mimpid : 0x20181004 > > mvendorid, marchid values match the register description in u74 manual. > > mimpid seems to be ok, through i can't find exact in U74/Unmatched docs. SiFive main website -> Products -> Documentation -> U74-MC Core Complex Manual -> Page 274: B.2 Machine Implementation ID Register (mimpid). This mimpid value is not in the table thus it's most likely not part of a particular U74 generator release. Looking at this value we could assume that U74 cores within FU740 predates the general availability. Cheers, david > > Tested-by: Nikita Shubin <n.shubin@yadro.com> > > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > arch/riscv/kernel/cpu.c | 51 > > +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 > > insertions(+) > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index fba9e9f46a8c..c037b8691bbb 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -3,10 +3,13 @@ > > * Copyright (C) 2012 Regents of the University of California > > */ > > > > +#include <linux/cpu.h> > > #include <linux/init.h> > > #include <linux/seq_file.h> > > #include <linux/of.h> > > +#include <asm/csr.h> > > #include <asm/hwcap.h> > > +#include <asm/sbi.h> > > #include <asm/smp.h> > > #include <asm/pgtable.h> > > > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node > > *node) } > > > > #ifdef CONFIG_PROC_FS > > + > > +struct riscv_cpuinfo { > > + unsigned long mvendorid; > > + unsigned long marchid; > > + unsigned long mimpid; > > +}; > > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > + > > +static int riscv_cpuinfo_starting(unsigned int cpu) > > +{ > > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > > + > > +#if defined(CONFIG_RISCV_SBI) > > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > > +#elif defined(CONFIG_RISCV_M_MODE) > > + ci->mvendorid = csr_read(CSR_MVENDORID); > > + ci->marchid = csr_read(CSR_MARCHID); > > + ci->mimpid = csr_read(CSR_MIMPID); > > +#else > > + ci->mvendorid = 0; > > + ci->marchid = 0; > > + ci->mimpid = 0; > > +#endif > > + > > + return 0; > > +} > > + > > +static int __init riscv_cpuinfo_init(void) > > +{ > > + int ret; > > + > > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > > "riscv/cpuinfo:starting", > > + riscv_cpuinfo_starting, NULL); > > + if (ret < 0) { > > + pr_err("cpuinfo: failed to register hotplug > > callbacks.\n"); > > + return ret; > > + } > > + > > + return 0; > > +} > > +device_initcall(riscv_cpuinfo_init); > > + > > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > > { \ > > .uprop = #UPROP, \ > > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > > { > > unsigned long cpu_id = (unsigned long)v - 1; > > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, > > cpu_id); const char *compat, *isa; > > > > seq_printf(m, "processor\t: %lu\n", cpu_id); > > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > > if (!of_property_read_string(node, "compatible", &compat) > > && strcmp(compat, "riscv")) > > seq_printf(m, "uarch\t\t: %s\n", compat); > > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > > seq_puts(m, "\n"); > > of_node_put(node); > > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Palmer, On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@ventanamicro.com> wrote: > > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> Can this patch be considered for 5.20 ? Regards, Anup > --- > arch/riscv/kernel/cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..c037b8691bbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -3,10 +3,13 @@ > * Copyright (C) 2012 Regents of the University of California > */ > > +#include <linux/cpu.h> > #include <linux/init.h> > #include <linux/seq_file.h> > #include <linux/of.h> > +#include <asm/csr.h> > #include <asm/hwcap.h> > +#include <asm/sbi.h> > #include <asm/smp.h> > #include <asm/pgtable.h> > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node *node) > } > > #ifdef CONFIG_PROC_FS > + > +struct riscv_cpuinfo { > + unsigned long mvendorid; > + unsigned long marchid; > + unsigned long mimpid; > +}; > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > + > +static int riscv_cpuinfo_starting(unsigned int cpu) > +{ > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > + > +#if defined(CONFIG_RISCV_SBI) > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > +#elif defined(CONFIG_RISCV_M_MODE) > + ci->mvendorid = csr_read(CSR_MVENDORID); > + ci->marchid = csr_read(CSR_MARCHID); > + ci->mimpid = csr_read(CSR_MIMPID); > +#else > + ci->mvendorid = 0; > + ci->marchid = 0; > + ci->mimpid = 0; > +#endif > + > + return 0; > +} > + > +static int __init riscv_cpuinfo_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", > + riscv_cpuinfo_starting, NULL); > + if (ret < 0) { > + pr_err("cpuinfo: failed to register hotplug callbacks.\n"); > + return ret; > + } > + > + return 0; > +} > +device_initcall(riscv_cpuinfo_init); > + > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > { \ > .uprop = #UPROP, \ > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); > const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > seq_puts(m, "\n"); > of_node_put(node); > > -- > 2.34.1 >
Hey Anup, On 26/07/2022 12:57, Anup Patel wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Palmer, > > On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@ventanamicro.com> wrote: >> >> Identifying the underlying RISC-V implementation can be important >> for some of the user space applications. For example, the perf tool >> uses arch specific CPU implementation id (i.e. CPUID) to select a >> JSON file describing custom perf events on a CPU. >> >> Currently, there is no way to identify RISC-V implementation so we >> add mvendorid, marchid, and mimpid to /proc/cpuinfo output. >> >> Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > Can this patch be considered for 5.20 ? iirc I mentioned the consistency of using defined() for CONFIG_RISCV_SBI versus IS_ENABLED() elsewhere in arch/riscv/ but I don't recall a response. Thanks, Conor.
On Tue, Jul 26, 2022 at 7:10 PM <Conor.Dooley@microchip.com> wrote: > > Hey Anup, > > On 26/07/2022 12:57, Anup Patel wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Hi Palmer, > > > > On Mon, Jun 20, 2022 at 5:26 PM Anup Patel <apatel@ventanamicro.com> wrote: > >> > >> Identifying the underlying RISC-V implementation can be important > >> for some of the user space applications. For example, the perf tool > >> uses arch specific CPU implementation id (i.e. CPUID) to select a > >> JSON file describing custom perf events on a CPU. > >> > >> Currently, there is no way to identify RISC-V implementation so we > >> add mvendorid, marchid, and mimpid to /proc/cpuinfo output. > >> > >> Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > > > Can this patch be considered for 5.20 ? > > iirc I mentioned the consistency of using defined() for > CONFIG_RISCV_SBI versus IS_ENABLED() elsewhere in arch/riscv/ > but I don't recall a response. Sorry, I missed your comment. I will address and send v2 soon. Regards, Anup > > Thanks, > Conor.
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..c037b8691bbb 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -3,10 +3,13 @@ * Copyright (C) 2012 Regents of the University of California */ +#include <linux/cpu.h> #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/csr.h> #include <asm/hwcap.h> +#include <asm/sbi.h> #include <asm/smp.h> #include <asm/pgtable.h> @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node *node) } #ifdef CONFIG_PROC_FS + +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +static int riscv_cpuinfo_starting(unsigned int cpu) +{ + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); + +#if defined(CONFIG_RISCV_SBI) + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); +#elif defined(CONFIG_RISCV_M_MODE) + ci->mvendorid = csr_read(CSR_MVENDORID); + ci->marchid = csr_read(CSR_MARCHID); + ci->mimpid = csr_read(CSR_MIMPID); +#else + ci->mvendorid = 0; + ci->marchid = 0; + ci->mimpid = 0; +#endif + + return 0; +} + +static int __init riscv_cpuinfo_init(void) +{ + int ret; + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", + riscv_cpuinfo_starting, NULL); + if (ret < 0) { + pr_err("cpuinfo: failed to register hotplug callbacks.\n"); + return ret; + } + + return 0; +} +device_initcall(riscv_cpuinfo_init); + #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ { \ .uprop = #UPROP, \ @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) { unsigned long cpu_id = (unsigned long)v - 1; struct device_node *node = of_get_cpu_node(cpu_id, NULL); + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); const char *compat, *isa; seq_printf(m, "processor\t: %lu\n", cpu_id); @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) seq_printf(m, "uarch\t\t: %s\n", compat); + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); seq_puts(m, "\n"); of_node_put(node);
Identifying the underlying RISC-V implementation can be important for some of the user space applications. For example, the perf tool uses arch specific CPU implementation id (i.e. CPUID) to select a JSON file describing custom perf events on a CPU. Currently, there is no way to identify RISC-V implementation so we add mvendorid, marchid, and mimpid to /proc/cpuinfo output. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/kernel/cpu.c | 51 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)