| Message ID | 20220629200732.4039258-1-conor@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: dts: microchip: hook up the mpfs' l2cache | expand |
On Wed, Jun 29, 2022 at 09:07:33PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The initial PolarFire SoC devicetree must have been forked off from > the fu540 one prior to the addition of l2cache controller support being > added there. When the controller node was added to mpfs.dtsi, it was > not hooked up to the CPUs & thus sysfs reports an incorrect cache > configuration. Hook it up. > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> > From: Conor Dooley <conor.dooley@microchip.com> > Date: Monday, 4 July 2022 at 10:04 > To: FPGA ESS Linux patches <FPGA-ESS-Linux-Patches@microchip.com> > Cc: Conor Dooley - M52691 <Conor.Dooley@microchip.com> > Subject: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache > > The initial PolarFire SoC devicetree must have been forked off from > the fu540 one prior to the addition of l2cache controller support being > added there. When the controller node was added to mpfs.dtsi, it was > not hooked up to the CPUs & thus sysfs reports an incorrect cache > configuration. Hook it up. > > Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index ed8739350587..2df555a57003 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -50,6 +50,7 @@ cpu1: cpu@1 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu1_intc: interrupt-controller { > @@ -77,6 +78,7 @@ cpu2: cpu@2 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu2_intc: interrupt-controller { > @@ -104,6 +106,7 @@ cpu3: cpu@3 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu3_intc: interrupt-controller { > @@ -131,6 +134,7 @@ cpu4: cpu@4 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>; > -- > 2.36.1
From: Conor Dooley <conor.dooley@microchip.com> On Wed, 29 Jun 2022 21:07:33 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The initial PolarFire SoC devicetree must have been forked off from > the fu540 one prior to the addition of l2cache controller support being > added there. When the controller node was added to mpfs.dtsi, it was > not hooked up to the CPUs & thus sysfs reports an incorrect cache > configuration. Hook it up. > > [...] Applied to dt-fixes, thanks! [1/1] riscv: dts: microchip: hook up the mpfs' l2cache https://git.kernel.org/conor/c/efa310ba0071 Thanks, Conor.
On Wed, 29 Jun 2022 13:07:33 PDT (-0700), conor@kernel.org wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The initial PolarFire SoC devicetree must have been forked off from > the fu540 one prior to the addition of l2cache controller support being > added there. When the controller node was added to mpfs.dtsi, it was > not hooked up to the CPUs & thus sysfs reports an incorrect cache > configuration. Hook it up. > > Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") I just noticed this as I was looking over the PR I just sent, but since you're sending PRs I'm no longer re-writing your commits and thus I won't be adding stable CCs. If you want stuff CC'd to stable you'll have to either add it to the tags in the commit, or do so after the fact. > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index 3095d08453a1..496d3b7642bd 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -50,6 +50,7 @@ cpu1: cpu@1 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu1_intc: interrupt-controller { > @@ -77,6 +78,7 @@ cpu2: cpu@2 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu2_intc: interrupt-controller { > @@ -104,6 +106,7 @@ cpu3: cpu@3 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > > cpu3_intc: interrupt-controller { > @@ -131,6 +134,7 @@ cpu4: cpu@4 { > riscv,isa = "rv64imafdc"; > clocks = <&clkcfg CLK_CPU>; > tlb-split; > + next-level-cache = <&cctrllr>; > status = "okay"; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>;
On 15/07/2022 18:32, Palmer Dabbelt wrote: > On Wed, 29 Jun 2022 13:07:33 PDT (-0700), conor@kernel.org wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> The initial PolarFire SoC devicetree must have been forked off from >> the fu540 one prior to the addition of l2cache controller support being >> added there. When the controller node was added to mpfs.dtsi, it was >> not hooked up to the CPUs & thus sysfs reports an incorrect cache >> configuration. Hook it up. >> >> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") > > I just noticed this as I was looking over the PR I just sent, but since you're sending PRs I'm no longer re-writing your commits and thus I won't be adding stable CCs. If you want stuff CC'd to stable you'll have to either add it to the tags in the commit, or do so after the fact. Or option 3, Sasha AUTOSELs it :) Good point though, I'll make sure to tack on the CC:stable where needed. I *think* that I have not done this isn't the worst thing in the world since it is only two patches & only one kernel to backport it to, but I'll make sure to do it going forward. Thanks Palmer.
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 3095d08453a1..496d3b7642bd 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -50,6 +50,7 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu1_intc: interrupt-controller { @@ -77,6 +78,7 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu2_intc: interrupt-controller { @@ -104,6 +106,7 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu3_intc: interrupt-controller { @@ -131,6 +134,7 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>;