From patchwork Mon Jul 4 11:45:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12905174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78DF6C43334 for ; Mon, 4 Jul 2022 11:51:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BLPcff1myXJ2ygKx+sBrj+tKB9L34u4PHk/DQ8s/av0=; b=0/yJ+V9pngUq5j nnJ6Sb2S9BXGduO1WEjFqrKMDDlkW1ytiO6Q/RiNi6JNepwr1W068dhFvbNCUVgCM/nu0ivCMUXaC CI7dCUR9hMzIn0YHNQuyGWHMvrx17Si9WaXO4NJWIxOawJjKL4nTtHTBWrc1w9WOah2zUClxcgLPz /4OyRuL3QeEOoKwpiVvFfSA4lsxRWch5kQ5a0tvGinQ31cJCK7rbq4u3dzdoqmeJBoW6xurtogdNY V97gWkMDOx5PyfvVJrmGm375Kn3VeFmLY7EgOHlkDnzaKssjBqQRGL8eSkLKn7KI5Qv6bMiga7D3t RM8uoNnmFF5+RUKwHHGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8KbY-0087c3-Br; Mon, 04 Jul 2022 11:51:04 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8KWo-0081Ee-Au for linux-riscv@lists.infradead.org; Mon, 04 Jul 2022 11:46:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656935170; x=1688471170; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NL1XdhwWv4eZJEkhqkXDdPRC7SJOg8Mko/Ziu/ZBb+M=; b=c6PDQC62w4ca682ubsuMbtUtsjVWue3UajZ508U3ISibbzXMOKYx+4qr 4cNBX8b7trZlL9Urd37iQquTvaVvRcdTd7cGp36DurFczYZ11K/wup0OI 1Hh9oZA8332E6NE4mDPWIHREy2l16kFa8321zQL33LapqGdzmjwQJLHEQ /PAmCV+rqYSAku6ugdIPciN+4jb86RET6mohnTkwGBItfVFLVV/P+8e2c 54ffaeNVhAst3x94Qg3vXoEFR4gnBk8PX1XFTuFMnLH7oREvmWQ8kZYlr 7snbjU/y5vJlRyNJNW20K8DbpCi9fdbrNKnvYsBIo7gvG9hqM7qO0ymYV Q==; X-IronPort-AV: E=Sophos;i="5.92,243,1650956400"; d="scan'208";a="102905919" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Jul 2022 04:46:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 4 Jul 2022 04:46:09 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 4 Jul 2022 04:46:06 -0700 From: Conor Dooley To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Nicolas Ferre , Claudiu Beznea CC: , , , , "Conor Dooley" Subject: [net-next PATCH v2 2/5] net: macb: add polarfire soc reset support Date: Mon, 4 Jul 2022 12:45:09 +0100 Message-ID: <20220704114511.1892332-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220704114511.1892332-1-conor.dooley@microchip.com> References: <20220704114511.1892332-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_044610_468953_3BF7263B X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To date, the Microchip PolarFire SoC (MPFS) has been using the cdns,macb compatible, however the generic device does not have reset support. Add a new compatible & .data for MPFS to hook into the reset functionality added for zynqmp support (and make the zynqmp init function generic in the process). Signed-off-by: Conor Dooley --- drivers/net/ethernet/cadence/macb_main.c | 26 ++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index d89098f4ede8..d43bcf256b02 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4689,34 +4689,32 @@ static const struct macb_config np4_config = { .usrio = &macb_default_usrio, }; -static int zynqmp_init(struct platform_device *pdev) +static int init_reset_optional(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); struct macb *bp = netdev_priv(dev); int ret; if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { - /* Ensure PS-GTR PHY device used in SGMII mode is ready */ + /* Ensure PHY device used in SGMII mode is ready */ bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL); if (IS_ERR(bp->sgmii_phy)) { ret = PTR_ERR(bp->sgmii_phy); dev_err_probe(&pdev->dev, ret, - "failed to get PS-GTR PHY\n"); + "failed to get SGMII PHY\n"); return ret; } ret = phy_init(bp->sgmii_phy); if (ret) { - dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n", + dev_err(&pdev->dev, "failed to init SGMII PHY: %d\n", ret); return ret; } } - /* Fully reset GEM controller at hardware level using zynqmp-reset driver, - * if mapped in device tree. - */ + /* Fully reset controller at hardware level if mapped in device tree */ ret = device_reset_optional(&pdev->dev); if (ret) { dev_err_probe(&pdev->dev, ret, "failed to reset controller"); @@ -4737,7 +4735,7 @@ static const struct macb_config zynqmp_config = { MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, .dma_burst_length = 16, .clk_init = macb_clk_init, - .init = zynqmp_init, + .init = init_reset_optional, .jumbo_max_len = 10240, .usrio = &macb_default_usrio, }; @@ -4751,6 +4749,17 @@ static const struct macb_config zynq_config = { .usrio = &macb_default_usrio, }; +static const struct macb_config mpfs_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | + MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = init_reset_optional, + .usrio = &macb_default_usrio, + .jumbo_max_len = 10240, +}; + static const struct macb_config sama7g5_gem_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | MACB_CAPS_MIIONRGMII, @@ -4787,6 +4796,7 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, { .compatible = "cdns,zynq-gem", .data = &zynq_config }, { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, + { .compatible = "microchip,mpfs-macb", .data = &mpfs_config }, { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, { /* sentinel */ }