From patchwork Fri Jul 8 14:39:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12911243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEA4BCCA481 for ; Fri, 8 Jul 2022 14:39:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RORyfG/cUy75aTM2mnKvSP6EDXJKd7HiISTUCYAfTnw=; b=cqRI7ZZzM0wy34 ncgBGsDbt3Kzd17ZJoLlEEOj3AeRfED/nq5t5Q9W2BXjw6jrHywL/0StMcf0W8q6Akh6Q+3QpsP97 cajtPwBEEP9likywjpZmpDii2RPQVlTgFlO9DbqF5o7yiYgWk/LZ5FzbDQUcAQMyOO5WHUkDp3q6X DLEtTZn+a5QGi1EF9fuhYq0y2BIQqnZhVKXkeXvbIThNL3UYysxe3whvCXsFUD2H+n/zXF4Pb7NNb 6Ki8ZIrX08oz/rgcR2Rhl7gIcwbnquAreVIYYsJYmjyBGxHGLtSaSTlPfs1MBtVo+qAAG5qIwlmR7 6/ErfGOcDHb0IrF2iAmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9p8n-004B9f-Eo; Fri, 08 Jul 2022 14:39:33 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9p8k-004B8X-Q9 for linux-riscv@lists.infradead.org; Fri, 08 Jul 2022 14:39:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657291170; x=1688827170; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E7lc4EnKiZ1cJys8i7k2b1wZuaqqZKmkVBwqdNfKks0=; b=LhpfRT59sFVc0mmuWcCHL6n2ZjNied8qBG45EKgXhVO9ZTZ4go6gPNa6 tv3ACyMV+U6XOI4pytvm+y8BxRWo9m2Q/VfMihiXy1fvEChIqDkSbE/hW IV9DwSIAhdlPYCPypMqfqWb171e9pmEIGwGgtJIBzQXa/kHrVvShXNLCM heyKmCxaLl3zlEqtIO2prxShC17SEm7Jofjzwto/bwk9kei/Ry28KEcPS sSdweuAva+aRB1z8TrxMfl5IFKo8snMwt0R6gl193akvb3n39hiV2qL5V NtwQZT6VpHLvaQ23e+HU1+TDOCqUxy5HbNq1PmR8rEkyT28p/G2WRSvUe w==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="181342726" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:39:29 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:39:27 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:39:25 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v5 2/4] riscv: dts: fix the icicle's #pwm-cells Date: Fri, 8 Jul 2022 15:39:21 +0100 Message-ID: <20220708143923.1129928-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708143923.1129928-1-conor.dooley@microchip.com> References: <20220708143923.1129928-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220708_073930_869088_65644B4C X-CRM114-Status: UNSURE ( 9.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..e09a13aef268 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; - #pwm-cells = <2>; + #pwm-cells = <3>; clocks = <&fabric_clk3>; status = "disabled"; };