diff mbox series

[RFC,V2,2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile

Message ID 20220710075644.738455-3-guoren@kernel.org (mailing list archive)
State New, archived
Headers show
Series Proof of concept for rv32 svpbmt support | expand

Commit Message

Guo Ren July 10, 2022, 7:56 a.m. UTC 
From: Guo Ren <guoren@linux.alibaba.com>

Make compile cleaner and don't reference the THEAD_PBMT data struct when
CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to
support rv32.

When current CONFIG_ERRATA_THEAD_PBMT is active in the alternative section
added to the build.
I.e. that translates to:

         .if IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)
         .pushsection .alternative, "a"
         ...

But, above can't affect the below:
	...
	"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),
	...
	"I"(ALT_THEAD_PBMT_SHIFT))

CONFIG_ERRATA_THEAD_PBMT is not clean enough, compiler still
process the  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT)" &
"I"(ALT_THEAD_PBMT_SHIFT).

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Heiko Stübner <heiko@sntech.de>
---
 arch/riscv/include/asm/errata_list.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 416ead0f9a65..47175d91773d 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -47,6 +47,8 @@  asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
  * in the default case.
  */
 #define ALT_SVPBMT_SHIFT 61
+
+#ifdef CONFIG_ERRATA_THEAD_PBMT
 #define ALT_THEAD_PBMT_SHIFT 59
 #define ALT_SVPBMT(_val, prot)						\
 asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
@@ -60,7 +62,6 @@  asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
 		  "I"(ALT_SVPBMT_SHIFT),				\
 		  "I"(ALT_THEAD_PBMT_SHIFT))
 
-#ifdef CONFIG_ERRATA_THEAD_PBMT
 /*
  * IO/NOCACHE memory types are handled together with svpbmt,
  * so on T-Head chips, check if no other memory type is set,
@@ -90,6 +91,14 @@  asm volatile(ALTERNATIVE(						\
 	  "I"(ALT_THEAD_PBMT_SHIFT)					\
 	: "t3")
 #else
+#define ALT_SVPBMT(_val, prot)						\
+asm(ALTERNATIVE("li %0, 0\t\nnop",					\
+		 "li %0, %1\t\nslli %0,%0,%2", 0,			\
+			CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT)	\
+		: "=r"(_val)						\
+		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
+		  "I"(ALT_SVPBMT_SHIFT))
+
 #define ALT_THEAD_PMA(_val)
 #endif