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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c410900b003a02cbf862esm7330892wmi.13.2022.07.11.11.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 11:44:10 -0700 (PDT) From: Conor Dooley To: Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] riscv: dts: starfive: add the missing monitor core Date: Mon, 11 Jul 2022 19:43:26 +0100 Message-Id: <20220711184325.1367393-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220711184325.1367393-1-mail@conchuod.ie> References: <20220711184325.1367393-1-mail@conchuod.ie> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220711_114412_071534_76E1E16C X-CRM114-Status: GOOD ( 11.14 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The JH7100 has a 32 bit monitor core that is missing from the device tree. Add it (and its cpu-map entry) to more accurately reflect the actual topology of the SoC. Signed-off-by: Conor Dooley Reviewed-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index c617a61e26e2..92fce5b66d3d 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -67,6 +67,23 @@ cpu1_intc: interrupt-controller { }; }; + E24: cpu@2 { + compatible = "sifive,e24", "riscv"; + reg = <2>; + device_type = "cpu"; + i-cache-block-size = <32>; + i-cache-sets = <256>; + i-cache-size = <16384>; + riscv,isa = "rv32imafc"; + status = "disabled"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu-map { cluster0 { core0 { @@ -76,6 +93,10 @@ core0 { core1 { cpu = <&U74_1>; }; + + core2 { + cpu = <&E24>; + }; }; }; };