From patchwork Tue Jul 12 14:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12915040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFCB8CCA47C for ; Tue, 12 Jul 2022 14:26:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dLq/6Nr79dGHIfWuxdEQK9+M31pHfctAZg4L4ifNVus=; b=L/aH50fMdqT4T+ +U+UH4Bs557hXS3P9oZpJh+TkAaDLu5XoWUzWTF1bgru4QBc84al73/+z8KVD1kGmBvwDV7IXwA90 8nUDcEcbm9Zld2Kqdi1oAH1B8KumWkocw4H37zC4zOKUGLmrwQKhMGVSy4dAFupm5rKxELmSWMpZ6 SlssY4zrD+Oaksr6xNAb8CS+nd/hDo3gUE4AmKBD/F/zsovs3zAPYYtHhyJwNZmAClvzLZW38FO4U /thB/Lod4w5T4pIWWXmP7nlcoUn2s9ebfiHKxJJPh3hYFB39AVm5G54NiuGzmpTNAU8OzDzeRpsZ3 tMmYdg6eHGPBMjEx9g5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBGq5-00BhH6-QM; Tue, 12 Jul 2022 14:26:13 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBGq1-00BhD4-3W for linux-riscv@lists.infradead.org; Tue, 12 Jul 2022 14:26:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657635968; x=1689171968; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGvCmSdLGhHwliGLCezI146iFxUX+rnhWkr8xC90Ykk=; b=S//76q8XD4x9KvIngqdT4FSMn1FxIr1xMs6l9ibX2ye9Ke5nxpW37LIe 313uHujmrKiJZIkZDVk5Opm3Li1Qc99udFAzwQ0z8QatxXSmnyGl6F7aY Sh5h37KZMWH90Kk5F2a0PJAXdFp7CcTXUiGZTCC+zXi/BZi0ohSpZ6+ck WRiiyVutIENlNRRRB23eHb/AfxfM34303AjKrgOLr4AIHZsb7Fw3Dv29W CbznXgqIq7281dj5kinTacwStjhcoRkCEdbgDM+1O0qlJy9W5//TaXPCs XvKQ4gIl5MqCtXvWqi51MHQYLcZr+tQg6ZU5sC1ex5/L9W9RjylXomr7x g==; X-IronPort-AV: E=Sophos;i="5.92,265,1650956400"; d="scan'208";a="181795577" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 07:26:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 07:26:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 07:26:05 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley , Rob Herring Subject: [PATCH v6 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Tue, 12 Jul 2022 15:25:54 +0100 Message-ID: <20220712142557.1773075-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220712142557.1773075-1-conor.dooley@microchip.com> References: <20220712142557.1773075-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220712_072609_169871_FA169CCD X-CRM114-Status: UNSURE ( 8.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: |