From patchwork Fri Aug 19 02:54:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12948249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F230C00140 for ; Fri, 19 Aug 2022 02:55:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xwS6ZHniKgMSgzT4bU+9oR9CmxsxAq61F6B6xmeQ2Ds=; b=CqAdkuqX8lwjnT TeUSzG/QwCt87IXTefra5DOwPyZnRTaZWoWjfYnx0IABPeJMr1yArLqDldslOeeyeYhjiMXxaHImY jXOTuhzfim8WsXadQv2ZMaTagGyJ4JkBMASy9HiBNRXE/jxN7q+qG6XTweYDjQdZMjKSkTitU1ojZ R4PcaL8T6tixjTJn+jojMLe3UzHTCjvhfVG6VAM2ud+0vIdEFMYfXEuquBmBhKOuErbJZVt4rc4LN pvAT9ezJBi0dLygezicxPIZ1MiNPbBSLPYCBGHWbnkcz7atG/vnPui+Ut/knksvXFOweoJe9Wh6P5 2Sh0KBsJYuDVWtzks1pA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOsA5-00F6nn-Rw; Fri, 19 Aug 2022 02:55:05 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOsA3-00F6mN-BU for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 02:55:04 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C4B4761492; Fri, 19 Aug 2022 02:55:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D8BEC43470; Fri, 19 Aug 2022 02:54:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660877701; bh=zq25NiQZz8wm9vgW2vXpq0gI46axFgfL/4UUq2ViQfE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a1wYDWHTZYUUxwYK/nj4O4YiPzJK1smkXVk3AeWY1NMnE69c+JJgpQc4q+VZnvVXB ZU2mPgiJie2AF9xGl9y8ujXfXJfN/GLRYvKusO7va6avKM+enAuxZsuES5oLyMKMPc b5y2ieqt+nrUoIw1Of58iJNwrCR//0ShziKdsrh66bm2TpoZuopmULalJVgdW5xPBy lRTqotAZTLAQ2tgMm1g/qjvonFJslubOOU3z2w68OizLn1Mq7aAl3cwfwYt+hqh9pt J2zE2TlQ67eX3dCYdP83LRsZ1yzECuFYONMTlY5ch5JnzuOSfxijxkyoxJtaXLgu9/ szCHY15Cs+b8w== From: guoren@kernel.org To: xianting.tian@linux.alibaba.com, palmer@dabbelt.com, heiko@sntech.de, guoren@kernel.org, conor.dooley@microchip.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, liaochang1@huawei.com, mick@ics.forth.gr, jszhang@kernel.org, Guo Ren , Will Deacon , AKASHI Takahiro Subject: [PATCH V3 1/3] riscv: kexec: Disable all interrupts in kexec crash path Date: Thu, 18 Aug 2022 22:54:42 -0400 Message-Id: <20220819025444.2121315-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819025444.2121315-1-guoren@kernel.org> References: <20220819025444.2121315-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220818_195503_521783_AD8057E4 X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren If a crash happens on cpu3 and all interrupts are binding on cpu0, the bad irq routing will cause a crash kernel which can't receive any irq. Because crash kernel won't clean up all harts' PLIC enable bits in enable registers. This patch is similar to 9141a003a491 ("ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path") and 78fd584cdec0 ("arm64: kdump: implement machine_crash_shutdown()"), and PowerPC also has the same mechanism. Fixes: fba8a8674f68 ("RISC-V: Add kexec support") Reviewed-by: Xianting Tian Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Will Deacon Cc: AKASHI Takahiro Cc: Nick Kossifidis --- arch/riscv/kernel/machine_kexec.c | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index ee79e6839b86..db41c676e5a2 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -15,6 +15,8 @@ #include /* For unreachable() */ #include /* For cpu_down() */ #include +#include +#include /* * kexec_image_info - Print received image details @@ -154,6 +156,37 @@ void crash_smp_send_stop(void) cpus_stopped = 1; } +static void machine_kexec_mask_interrupts(void) +{ + unsigned int i; + struct irq_desc *desc; + + for_each_irq_desc(i, desc) { + struct irq_chip *chip; + int ret; + + chip = irq_desc_get_chip(desc); + if (!chip) + continue; + + /* + * First try to remove the active state. If this + * fails, try to EOI the interrupt. + */ + ret = irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false); + + if (ret && irqd_irq_inprogress(&desc->irq_data) && + chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + + if (chip->irq_mask) + chip->irq_mask(&desc->irq_data); + + if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) + chip->irq_disable(&desc->irq_data); + } +} + /* * machine_crash_shutdown - Prepare to kexec after a kernel crash * @@ -169,6 +202,8 @@ machine_crash_shutdown(struct pt_regs *regs) crash_smp_send_stop(); crash_save_cpu(regs, smp_processor_id()); + machine_kexec_mask_interrupts(); + pr_info("Starting crashdump kernel...\n"); }