From patchwork Wed Aug 24 09:12:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12953078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7608C32792 for ; Wed, 24 Aug 2022 09:12:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dLq/6Nr79dGHIfWuxdEQK9+M31pHfctAZg4L4ifNVus=; b=h+/+6eUhVRsx4g wRFj59b77M2YFedIfjv6rS3kIlYramw6rOAjQGEbiTE5gOt0Hc7motMapaNJTv1JsJbEq5TrfyreI HVeAUi3QY2NX1nccZvV8uoOmRpG9SiKU1JwTo4wlnfxtCQl7gCiGhM6NPh7dmQlSm5F6GrGa+f3yZ HYSBE7oWd1r56QDIAY5+tnOZBjw4tXiywzjiAixmUo8t7bRekrNOsQ2jXzh+BD8UoWh7PXGouDJ0R qOSZ26MxhCSAzVP0X8C0QcM6E70Ee/sqgfCj3LjzJmQpJmPHGWRUheNetsequXhkcUt8RgdWYh7K5 jVLX2q5t7rQulWXUS+1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQmRK-00BgHl-R1; Wed, 24 Aug 2022 09:12:46 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oQmRI-00BgDe-6A for linux-riscv@lists.infradead.org; Wed, 24 Aug 2022 09:12:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661332365; x=1692868365; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGvCmSdLGhHwliGLCezI146iFxUX+rnhWkr8xC90Ykk=; b=WoiM8LZ23T4E+rNU3wgDbuGMMBbhdzF1U0ErPSt23Omi+JPr1gExsXTy rHRm6PiisVxTtrQC/Nnd9Xn2365uIHiTXp87xB3Xh87LVmThhCN9vNwN8 GUp6fYNB7eVL86cJ6yfQJuv7JyNvQTmDPe5hJfwLYtPLlg9QkWaONuBWz 0EWN+pabV7nwvk/8tXIGxGwOFsmZA/LW1GiL9+a3VnN3ltgAHHwezfW4/ 8ynn7vIe7BiAj6g8LnDJ0L81AhJDQarg/KYgmcw7YbYdwLWl5iehr8IS7 T2o3v2C/e5bMqMCn17QH4I5yyV7Jzlw5qJcMi36lbemtAyoB/hHs2ztn7 Q==; X-IronPort-AV: E=Sophos;i="5.93,260,1654585200"; d="scan'208";a="187831730" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2022 02:12:39 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 24 Aug 2022 02:12:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 24 Aug 2022 02:12:36 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Rob Herring" , Krzysztof Kozlowski CC: Daire McNamara , , , , , Conor Dooley , Rob Herring Subject: [PATCH v10 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Wed, 24 Aug 2022 10:12:12 +0100 Message-ID: <20220824091215.141577-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220824091215.141577-1-conor.dooley@microchip.com> References: <20220824091215.141577-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_021244_312543_C0621192 X-CRM114-Status: UNSURE ( 8.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: |