| Message ID | 20220830082620.1680602-1-ben.dooks@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | soc: sifive: ccache: reduce printing on init | expand |
On 30/08/2022 09:26, Ben Dooks wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > The driver prints out 6 lines on startup, which can easily be redcued > to two lines without losing any information. > > Note, to make the types work better, uint64_t has been replaced with > ULL to make the unsigned long long match the format in the print > statement. > > Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > --- > drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- > 1 file changed, 11 insertions(+), 14 deletions(-) > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > index 46ce33db7d30..65a10a6ee211 100644 > --- a/drivers/soc/sifive/sifive_ccache.c > +++ b/drivers/soc/sifive/sifive_ccache.c > @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) > > static void ccache_config_read(void) > { > - u32 regval, val; > - > - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > - val = regval & 0xFF; > - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); > - val = (regval & 0xFF00) >> 8; > - pr_info("CCACHE: No. of ways per bank: %d\n", val); > - val = (regval & 0xFF0000) >> 16; > - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); > - val = (regval & 0xFF000000) >> 24; > - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); > - > - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); > + u32 cfg; > + > + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > + > + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", > + (cfg & 0xff), (cfg >> 8) & 0xff, > + 1ULL << ((cfg >> 16) & 0xff), This is just BIT_ULL((cfg >> 16) & 0xff), no? Would be nice too if these were defined, so you'd have something like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff) I do like the cleanup of the uint64_t & cutting down on the prints though :) Again, it'd be nice if you and Zong could collaborate on a combined v2. Thanks, Conor. > + 1ULL << ((cfg >> 24) & 0xff)); > + > + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); > } > > static const struct of_device_id sifive_ccache_ids[] = { > -- > 2.35.1 >
On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote: > On 30/08/2022 09:26, Ben Dooks wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> The driver prints out 6 lines on startup, which can easily be redcued >> to two lines without losing any information. >> >> Note, to make the types work better, uint64_t has been replaced with >> ULL to make the unsigned long long match the format in the print >> statement. >> >> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> >> --- >> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- >> 1 file changed, 11 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c >> index 46ce33db7d30..65a10a6ee211 100644 >> --- a/drivers/soc/sifive/sifive_ccache.c >> +++ b/drivers/soc/sifive/sifive_ccache.c >> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) >> >> static void ccache_config_read(void) >> { >> - u32 regval, val; >> - >> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); >> - val = regval & 0xFF; >> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); >> - val = (regval & 0xFF00) >> 8; >> - pr_info("CCACHE: No. of ways per bank: %d\n", val); >> - val = (regval & 0xFF0000) >> 16; >> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); >> - val = (regval & 0xFF000000) >> 24; >> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); >> - >> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); >> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); >> + u32 cfg; >> + >> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); >> + >> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", >> + (cfg & 0xff), (cfg >> 8) & 0xff, >> + 1ULL << ((cfg >> 16) & 0xff), > > This is just BIT_ULL((cfg >> 16) & 0xff), no? > Would be nice too if these were defined, so you'd have something > like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff) > > I do like the cleanup of the uint64_t & cutting down on the prints > though :) Again, it'd be nice if you and Zong could collaborate on > a combined v2. I think even BIT_UL() would do here, if someone is going to make a cache bigger than 2GiB we'll probably be quite old by then, so v2 might have the last two values down as %lu. > Thanks, > Conor. > >> + 1ULL << ((cfg >> 24) & 0xff)); >> + >> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); >> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); >> } >> >> static const struct of_device_id sifive_ccache_ids[] = { >> -- >> 2.35.1 >> > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >
Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道： > > On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote: > > On 30/08/2022 09:26, Ben Dooks wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >> > >> The driver prints out 6 lines on startup, which can easily be redcued > >> to two lines without losing any information. > >> > >> Note, to make the types work better, uint64_t has been replaced with > >> ULL to make the unsigned long long match the format in the print > >> statement. > >> > >> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > >> --- > >> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- > >> 1 file changed, 11 insertions(+), 14 deletions(-) > >> > >> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > >> index 46ce33db7d30..65a10a6ee211 100644 > >> --- a/drivers/soc/sifive/sifive_ccache.c > >> +++ b/drivers/soc/sifive/sifive_ccache.c > >> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) > >> > >> static void ccache_config_read(void) > >> { > >> - u32 regval, val; > >> - > >> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > >> - val = regval & 0xFF; > >> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); > >> - val = (regval & 0xFF00) >> 8; > >> - pr_info("CCACHE: No. of ways per bank: %d\n", val); > >> - val = (regval & 0xFF0000) >> 16; > >> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); > >> - val = (regval & 0xFF000000) >> 24; > >> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); > >> - > >> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > >> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); > >> + u32 cfg; > >> + > >> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > >> + > >> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", > >> + (cfg & 0xff), (cfg >> 8) & 0xff, > >> + 1ULL << ((cfg >> 16) & 0xff), > > > > This is just BIT_ULL((cfg >> 16) & 0xff), no? > > Would be nice too if these were defined, so you'd have something > > like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff) > > > > I do like the cleanup of the uint64_t & cutting down on the prints > > though :) Again, it'd be nice if you and Zong could collaborate on > > a combined v2. > > I think even BIT_UL() would do here, if someone is going to make a > cache bigger than 2GiB we'll probably be quite old by then, so v2 > might have the last two values down as %lu. > Hi Ben, Thanks for your suggestion, If you don't mind, I will take this into my V2 patchset. > > Thanks, > > Conor. > > > >> + 1ULL << ((cfg >> 24) & 0xff)); > >> + > >> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > >> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); > >> } > >> > >> static const struct of_device_id sifive_ccache_ids[] = { > >> -- > >> 2.35.1 > >> > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 31/08/2022 06:22, Zong Li wrote: > Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道： >> >> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote: >>> On 30/08/2022 09:26, Ben Dooks wrote: >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>> >>>> The driver prints out 6 lines on startup, which can easily be redcued >>>> to two lines without losing any information. >>>> >>>> Note, to make the types work better, uint64_t has been replaced with >>>> ULL to make the unsigned long long match the format in the print >>>> statement. >>>> >>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> >>>> --- >>>> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- >>>> 1 file changed, 11 insertions(+), 14 deletions(-) >>>> >>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c >>>> index 46ce33db7d30..65a10a6ee211 100644 >>>> --- a/drivers/soc/sifive/sifive_ccache.c >>>> +++ b/drivers/soc/sifive/sifive_ccache.c >>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) >>>> >>>> static void ccache_config_read(void) >>>> { >>>> - u32 regval, val; >>>> - >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); >>>> - val = regval & 0xFF; >>>> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); >>>> - val = (regval & 0xFF00) >> 8; >>>> - pr_info("CCACHE: No. of ways per bank: %d\n", val); >>>> - val = (regval & 0xFF0000) >> 16; >>>> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); >>>> - val = (regval & 0xFF000000) >> 24; >>>> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); >>>> - >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); >>>> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); >>>> + u32 cfg; >>>> + >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); >>>> + >>>> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", >>>> + (cfg & 0xff), (cfg >> 8) & 0xff, >>>> + 1ULL << ((cfg >> 16) & 0xff), >>> >>> This is just BIT_ULL((cfg >> 16) & 0xff), no? >>> Would be nice too if these were defined, so you'd have something >>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff) >>> >>> I do like the cleanup of the uint64_t & cutting down on the prints >>> though :) Again, it'd be nice if you and Zong could collaborate on >>> a combined v2. >> >> I think even BIT_UL() would do here, if someone is going to make a >> cache bigger than 2GiB we'll probably be quite old by then, so v2 >> might have the last two values down as %lu. >> > > Hi Ben, > Thanks for your suggestion, If you don't mind, I will take this into > my V2 patchset. Thanks. I may well post v2 of this tomorrow with the BIT_ULL() suggestions from Conor, or even down to BIT_UL() and use %lu as noted. > >>> Thanks, >>> Conor. >>> >>>> + 1ULL << ((cfg >> 24) & 0xff)); >>>> + >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); >>>> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); >>>> } >>>> >>>> static const struct of_device_id sifive_ccache_ids[] = { >>>> -- >>>> 2.35.1 >>>> >>> >>> _______________________________________________ >>> linux-riscv mailing list >>> linux-riscv@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >> >> -- >> Ben Dooks http://www.codethink.co.uk/ >> Senior Engineer Codethink - Providing Genius >> >> https://www.codethink.co.uk/privacy.html >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Aug 31, 2022 at 11:55 PM Ben Dooks <ben.dooks@sifive.com> wrote: > > On 31/08/2022 06:22, Zong Li wrote: > > Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道： > >> > >> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote: > >>> On 30/08/2022 09:26, Ben Dooks wrote: > >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >>>> > >>>> The driver prints out 6 lines on startup, which can easily be redcued > >>>> to two lines without losing any information. > >>>> > >>>> Note, to make the types work better, uint64_t has been replaced with > >>>> ULL to make the unsigned long long match the format in the print > >>>> statement. > >>>> > >>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > >>>> --- > >>>> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- > >>>> 1 file changed, 11 insertions(+), 14 deletions(-) > >>>> > >>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > >>>> index 46ce33db7d30..65a10a6ee211 100644 > >>>> --- a/drivers/soc/sifive/sifive_ccache.c > >>>> +++ b/drivers/soc/sifive/sifive_ccache.c > >>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) > >>>> > >>>> static void ccache_config_read(void) > >>>> { > >>>> - u32 regval, val; > >>>> - > >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > >>>> - val = regval & 0xFF; > >>>> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); > >>>> - val = (regval & 0xFF00) >> 8; > >>>> - pr_info("CCACHE: No. of ways per bank: %d\n", val); > >>>> - val = (regval & 0xFF0000) >> 16; > >>>> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); > >>>> - val = (regval & 0xFF000000) >> 24; > >>>> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); > >>>> - > >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > >>>> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); > >>>> + u32 cfg; > >>>> + > >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); > >>>> + > >>>> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", > >>>> + (cfg & 0xff), (cfg >> 8) & 0xff, > >>>> + 1ULL << ((cfg >> 16) & 0xff), > >>> > >>> This is just BIT_ULL((cfg >> 16) & 0xff), no? > >>> Would be nice too if these were defined, so you'd have something > >>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff) > >>> > >>> I do like the cleanup of the uint64_t & cutting down on the prints > >>> though :) Again, it'd be nice if you and Zong could collaborate on > >>> a combined v2. > >> > >> I think even BIT_UL() would do here, if someone is going to make a > >> cache bigger than 2GiB we'll probably be quite old by then, so v2 > >> might have the last two values down as %lu. > >> > > > > Hi Ben, > > Thanks for your suggestion, If you don't mind, I will take this into > > my V2 patchset. > > Thanks. > > I may well post v2 of this tomorrow with the BIT_ULL() suggestions > from Conor, or even down to BIT_UL() and use %lu as noted. > No problem Ben. Could you please also add me in the thread of your v2, then I can take it and send out my v2 patchset. Thanks. > > > >>> Thanks, > >>> Conor. > >>> > >>>> + 1ULL << ((cfg >> 24) & 0xff)); > >>>> + > >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); > >>>> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); > >>>> } > >>>> > >>>> static const struct of_device_id sifive_ccache_ids[] = { > >>>> -- > >>>> 2.35.1 > >>>> > >>> > >>> _______________________________________________ > >>> linux-riscv mailing list > >>> linux-riscv@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-riscv > >>> > >> > >> -- > >> Ben Dooks http://www.codethink.co.uk/ > >> Senior Engineer Codethink - Providing Genius > >> > >> https://www.codethink.co.uk/privacy.html > >> > >> > >> _______________________________________________ > >> linux-riscv mailing list > >> linux-riscv@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-riscv >
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 46ce33db7d30..65a10a6ee211 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) static void ccache_config_read(void) { - u32 regval, val; - - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val = regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val = (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val = (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val = (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + (cfg & 0xff), (cfg >> 8) & 0xff, + 1ULL << ((cfg >> 16) & 0xff), + 1ULL << ((cfg >> 24) & 0xff)); + + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = {
The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-)