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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With newer cores such as the p550, the SiFive composable cache can be a level 3 cache. Update the cache level to be one of 2 or 3. Signed-off-by: Ben Dooks Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml index 1a64a5384e36..6190deb65455 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -45,7 +45,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048]