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[99.152.116.91]) by smtp.gmail.com with ESMTPSA id l5-20020a170903244500b00177f32b1a32sm21074410pls.271.2022.09.19.15.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 15:39:29 -0700 (PDT) From: Olof Johansson To: Greg Kroah-Hartman Cc: Jiri Slaby , linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Olof Johansson , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley Subject: [PATCH] serial: sifive: enable clocks for UART when probed Date: Mon, 19 Sep 2022 15:39:15 -0700 Message-Id: <20220919223915.5146-1-olof@lixom.net> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220919_153931_484398_3F1326F3 X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When the PWM driver was changed to disable clocks if no PWMs are enabled, it ended up also disabling the shared parent with the UART, since the UART doesn't do any clock enablement on its own. To avoid these surprises, add clk_prepare_enable/clk_disable_unprepare calls. Fixes: ace41d7564e655 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM") Cc: Uwe Kleine-König Cc: Emil Renner Berthing Cc: Palmer Dabbelt Cc: Paul Walmsley Signed-off-by: Olof Johansson --- drivers/tty/serial/sifive.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c index 5c3a07546a58..751f98068806 100644 --- a/drivers/tty/serial/sifive.c +++ b/drivers/tty/serial/sifive.c @@ -950,23 +950,28 @@ static int sifive_serial_probe(struct platform_device *pdev) dev_err(&pdev->dev, "unable to find controller clock\n"); return PTR_ERR(clk); } + clk_prepare_enable(clk); id = of_alias_get_id(pdev->dev.of_node, "serial"); if (id < 0) { dev_err(&pdev->dev, "missing aliases entry\n"); - return id; + r = id; + goto probe_out1; } #ifdef CONFIG_SERIAL_SIFIVE_CONSOLE if (id > SIFIVE_SERIAL_MAX_PORTS) { dev_err(&pdev->dev, "too many UARTs (%d)\n", id); - return -EINVAL; + r = -EINVAL; + goto probe_out1; } #endif ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); - if (!ssp) - return -ENOMEM; + if (!ssp) { + r = -ENOMEM; + goto probe_out1; + } ssp->port.dev = &pdev->dev; ssp->port.type = PORT_SIFIVE_V0; @@ -1028,6 +1033,7 @@ static int sifive_serial_probe(struct platform_device *pdev) probe_out2: clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); probe_out1: + clk_disable_unprepare(clk); return r; }