From patchwork Thu Oct 6 07:08:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13000024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13859C433FE for ; Thu, 6 Oct 2022 07:18:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zzWa1yUUf+emir6+AeClq364HWpS/DghJmrvzxZ8Yq0=; b=pRdXtMs7Z90Thn CsFr5oDhbXNJksEI04itw082ytdtuvV6Snrc/dkFhgw+0ZN7L4M66qo4b7znxQR1AdfrVDv3eFn4d Tur/1tYRbimb34/5w1pBuLGUmoLFRL9uY/T5GGCkD/VGIMGoVRnOSyEu5M1MhePyB5Fyd/j0s8erD NNUDCT3piBawvh/mv7Tn85OQlA7DGns8oWua8BltO8gDuyRgyRHfutu833dB0B/flGmIu4BMvQHh3 4YdBPp5MntTW3gxmHE00knYUb/+aWv/qQNAI2shV3C2mP9ZBB9+5glOK1jPBE76tbFu/xt5tCQLhe DXgT0tuMFOuEDozCbP6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ogL92-000MiU-It; Thu, 06 Oct 2022 07:18:12 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ogL8t-000MYZ-BS for linux-riscv@lists.infradead.org; Thu, 06 Oct 2022 07:18:04 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EB03661861; Thu, 6 Oct 2022 07:18:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A24A9C433C1; Thu, 6 Oct 2022 07:18:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040682; bh=CDY3LOHif93dA/5GcjxLOgr3s2+BMCkMTymaYNZuiyA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qRm9LVZBrunvLnYytd4pxa3rFq57nHfJ9HsOwpVTeWPTZL9sFAJFrYSAejIdUkx2+ +YWVA9Eo3yES9EQw9vR36Re1DZf8dhjtceMd03N6u3RCK+4X2qLONGZEcfnYBLpDKL hwPWSOWrkWM9W32TBw54oRrYC8Dk0URo+cdsVvMIqxw3t3RKe5+AQWn+M4rwwHOyS9 LCNF+pVn+aEpOcKXGNhIhkrtPk6VZs8B8J/PSxyZ/1pv4uwg9411eHxebQnt0XrWbb yGu+Tcq7FLQy8KgWezDl4mFSASslMOxJxrPovxMLCwChU97FyjTPIc0grP8kx8o+cM BxDCWLzehBhzQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Date: Thu, 6 Oct 2022 15:08:18 +0800 Message-Id: <20221006070818.3616-9-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221006_001803_495784_A9FBB373 X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org All users have switched to riscv_has_extension_*, removed unused definitions, vars and related setting code. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 28 ---------------------------- arch/riscv/kernel/cpufeature.c | 9 --------- 2 files changed, 37 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 54b88ee6cae1..f52fbc121ebe 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -62,18 +62,6 @@ enum { extern unsigned long elf_hwcap; - -/* - * This enum represents the logical ID for each RISC-V ISA extension static - * keys. We can use static key to optimize code path if some ISA extensions - * are available. - */ -enum riscv_isa_ext_key { - RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, - RISCV_ISA_EXT_KEY_MAX, -}; - struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; @@ -81,22 +69,6 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; -extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX]; - -static __always_inline int riscv_isa_ext2key(int num) -{ - switch (num) { - case RISCV_ISA_EXT_f: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_d: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_ZIHINTPAUSE: - return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; - default: - return -EINVAL; - } -} - static __always_inline bool riscv_has_extension_likely(const unsigned long ext) { diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2b1f18f97253..6bc3fb749274 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -28,9 +28,6 @@ unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; -DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); -EXPORT_SYMBOL(riscv_isa_ext_keys); - /** * riscv_isa_extension_base() - Get base extension word * @@ -242,12 +239,6 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); - - for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) { - j = riscv_isa_ext2key(i); - if (j >= 0) - static_branch_enable(&riscv_isa_ext_keys[j]); - } } #ifdef CONFIG_RISCV_ALTERNATIVE