Message ID | 20221017084411.3557098-2-yangyingliang@huawei.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | [1/2] soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() | expand |
Reviewed-by: Conor Dooley <conor.dooley@microchip.com> On Mon, Oct 17, 2022 at 04:44:11PM +0800, Yang Yingliang wrote: > Add missing free_irq() before return error from sifive_ccache_init(). > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> > --- > drivers/soc/sifive/sifive_ccache.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > index 25019c16d8ae..98269d056728 100644 > --- a/drivers/soc/sifive/sifive_ccache.c > +++ b/drivers/soc/sifive/sifive_ccache.c > @@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void) > NULL); > if (rc) { > pr_err("Could not request IRQ %d\n", g_irq[i]); > - goto err_unmap; > + goto err_free_irq; > } > } > > @@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void) > #endif > return 0; > > +err_free_irq: > + while (--i >= 0) > + free_irq(g_irq[i], NULL); > err_unmap: > iounmap(ccache_base); > return rc; > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 25019c16d8ae..98269d056728 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void) NULL); if (rc) { pr_err("Could not request IRQ %d\n", g_irq[i]); - goto err_unmap; + goto err_free_irq; } } @@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void) #endif return 0; +err_free_irq: + while (--i >= 0) + free_irq(g_irq[i], NULL); err_unmap: iounmap(ccache_base); return rc;
Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> --- drivers/soc/sifive/sifive_ccache.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)