From patchwork Wed Oct 19 12:53:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13011704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D25E5C4332F for ; Wed, 19 Oct 2022 12:54:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lhBRe8zZsRy+Yyu/BlzwxPgxT/cUnua0TdR+WrJqSrc=; b=jv/gCTCCxpFg7R oUybB9pDUM67NkbFfCitwKmdukXe3odBLy3GioLQRY4NpYe50w2nwFFC5nZ8nhGAdQH5wlw6HNt5F 7dD3P4+E80WcJH0DgRUBRkhT+EV/T1KRMHO/Piqmc2lK6j9TwTzRfYs+/s/Xv8wSUyhHkLaae5qZu VF9oI4bNZjQQ71nZlU2xykDFuRVqjhZ2rSqSR90ypqiJ8NPSdXiDNSL9abv8CXvjDEGYcUOks/JSA HTyxwq4m+qlq0gakFhxaXilWIKZmnSMhJYEa/vRPwlefNWp8Ie+Arfoak4HM+N1zfM2gbib1Vmfvj 2yCO4W9KFV3uWF4f2L8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ol8a0-001lki-Ua; Wed, 19 Oct 2022 12:53:52 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ol8Zg-001lPo-IZ; Wed, 19 Oct 2022 12:53:34 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666184012; x=1697720012; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7nRf7HpxMobG7tiEk47jyd5TdB9jkpmn4TMYC/GrBxo=; b=1vYnV1MFYAW9JtYJUhnmE5antDpNnZqvD/Lss/lXCulC+eQGbvC7HhWY 4wH/2ueiBsNJqKZKYcYPBEQZd7dsuoRb9dGx8TPwbgZIWVNEbvqc7MJDy WViSZwSp8vKrlLidUcWc8KxjAir5uurGdy6mRyuC68qVuR4bUabdOXO8Q Tg6PIJivrnA1cVg6ax1/+XXptAciJwicbBnvKuJZiUeeeGJbzi+axKr6H zsGqyQzfMHAcNHKQDqPV19Ia+4814gWxtfaYEddTVCIAJtakuym64Clqj KwkITCZ7AxfNOEP1twUlVQImN3CqVkfTnBw4/IiYVWb3H4FUX1XHfPOW+ A==; X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="185504889" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Oct 2022 05:53:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 19 Oct 2022 05:53:31 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 19 Oct 2022 05:53:29 -0700 From: Conor Dooley To: CC: , , , , , , , , , , , Atish Patra Subject: [PATCH 5.10 2/2] riscv: topology: fix default topology reporting Date: Wed, 19 Oct 2022 13:53:03 +0100 Message-ID: <20221019125303.2845522-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221019125303.2845522-1-conor.dooley@microchip.com> References: <20221019125303.2845522-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221019_055332_680194_905F99B7 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org commit fbd92809997a391f28075f1c8b5ee314c225557c upstream. RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree. Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology. On a PolarFire SoC, which should have 4 harts with a thread each, lstopo currently reports: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3) Adding calls to store_cpu_topology() in {boot,smp} hart bringup code results in the correct topolgy being reported: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3) CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Reviewed-by: Sudeep Holla Reviewed-by: Atish Patra Signed-off-by: Conor Dooley --- I just resolved the conflicts, which was mainly removing mentions of NUMA. Tested in QEMU only. --- arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1b894c327578..557c4a8c4087 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -35,7 +35,7 @@ config RISCV select CLINT_TIMER if !MMU select COMMON_CLK select EDAC_SUPPORT - select GENERIC_ARCH_TOPOLOGY if SMP + select GENERIC_ARCH_TOPOLOGY select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS select GENERIC_EARLY_IOREMAP diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0b04e0eae3ab..0e0aed380e28 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -46,6 +46,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpuid; int ret; + store_cpu_topology(smp_processor_id()); + /* This covers non-smp usecase mandated by "nosmp" option */ if (max_cpus == 0) return; @@ -152,8 +154,8 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm = mm; + store_cpu_topology(curr_cpuid); notify_cpu_starting(curr_cpuid); - update_siblings_masks(curr_cpuid); set_cpu_online(curr_cpuid, 1); /*