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[31.30.173.61]) by smtp.gmail.com with ESMTPSA id r2-20020a1709061ba200b0078d76ee7543sm11398573ejg.222.2022.10.21.03.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 03:59:11 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: Palmer Dabbelt , Paul Walmsley , Albert Ou , Conor Dooley , Heiko Stuebner , Anup Patel , Atish Patra Subject: [PATCH 3/3] RISC-V: Ensure Zicbom has a valid block size Date: Fri, 21 Oct 2022 12:59:05 +0200 Message-Id: <20221021105905.206385-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221021105905.206385-1-ajones@ventanamicro.com> References: <20221021105905.206385-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221021_035915_647021_0FDA7F2E X-CRM114-Status: GOOD ( 12.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When a DT puts zicbom in the isa string, but does not provide a block size, ALT_CMO_OP() will attempt to do cache operations on address zero since the start address will be ANDed with zero. We can't simply BUG() in riscv_init_cbom_blocksize() when we fail to find a block size because the failure will happen before logging works, leaving users to scratch their heads as to why the boot hung. Instead, ensure Zicbom is disabled and output an error which will hopefully alert people that the DT needs to be fixed. While at it, add a check that the block size is a power-of-2 too. Signed-off-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 220be7222129..a4430a77df53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,20 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); static bool riscv_isa_extension_check(int id) { + switch (id) { + case RISCV_ISA_EXT_ZICBOM: + if (!riscv_cbom_block_size) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) + pr_err("cbom-block-size not found, cannot use Zicbom\n"); + return false; + } else if (!is_power_of_2(riscv_cbom_block_size)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) + pr_err("cbom-block-size is not a power-of-2, cannot use Zicbom\n"); + return false; + } + return true; + } + return true; }