@@ -17,6 +17,13 @@ static inline void local_flush_icache_all(void)
static inline void flush_dcache_page(struct page *page)
{
+ /*
+ * HugeTLB pages are always fully mapped and only head page will be
+ * set PG_dcache_clean (see comments in flush_icache_pte()).
+ */
+ if (PageHuge(page))
+ page = compound_head(page);
+
if (test_bit(PG_dcache_clean, &page->flags))
clear_bit(PG_dcache_clean, &page->flags);
}
@@ -82,6 +82,13 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
+ /*
+ * HugeTLB pages are always fully mapped, so only setting head page's
+ * PG_dcache_clean flag is enough.
+ */
+ if (PageHuge(page))
+ page = compound_head(page);
+
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
flush_icache_all();
}
HugeTLB pages are always fully mapped, so only setting head page's PG_dcache_clean flag is enough. This refers to the following link: https://lore.kernel.org/lkml/20220331065640.5777-2-songmuchun@bytedance.com/ Signed-off-by: Tong Tiangen <tongtiangen@huawei.com> --- arch/riscv/include/asm/cacheflush.h | 7 +++++++ arch/riscv/mm/cacheflush.c | 7 +++++++ 2 files changed, 14 insertions(+)