| Message ID | 20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/apply | fail | Patch does not apply to for-next |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > Single). > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > can be used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - PLIC > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v4 -> v5 > * Fixed riscv,ndev value (should be 511) > * Reworked completely (sort of new patch) > > v3 -> v4 > * No change > > v2 -> v3 > * Fixed clock entry for CPU core > * Fixed timebase frequency to 12MHz > * Fixed sorting of the nodes > * Included RB tags > > v1 -> v2 > * Dropped including makefile change > * Updated ndev count > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > new file mode 100644 > index 000000000000..50134be548f5 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SoC > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > + > +#include <arm64/renesas/r9a07g043.dtsi> The initial patch shouldn't be broken. Combine them together with the minimal components and add others late. Don't separate the DTS files. > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <12000000>; > + > + cpu0: cpu@0 { > + compatible = "andestech,ax45mp", "riscv"; > + device_type = "cpu"; > + reg = <0x0>; > + status = "okay"; > + riscv,isa = "rv64imafdc"; > + mmu-type = "riscv,sv39"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <0x40>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <0x40>; > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > + > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > +}; > + > +&soc { > + interrupt-parent = <&plic>; > + > + plic: interrupt-controller@12c00000 { > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > + #interrupt-cells = <2>; > + #address-cells = <0>; > + riscv,ndev = <511>; > + interrupt-controller; > + reg = <0x0 0x12c00000 0 0x400000>; > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; Ditto, Where is cpg? in r9a07g043.dtsi? > + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; > + }; > +}; > -- > 2.25.1 >
Hi Guo, Thank you for the review. On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - PLIC > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v4 -> v5 > > * Fixed riscv,ndev value (should be 511) > > * Reworked completely (sort of new patch) > > > > v3 -> v4 > > * No change > > > > v2 -> v3 > > * Fixed clock entry for CPU core > > * Fixed timebase frequency to 12MHz > > * Fixed sorting of the nodes > > * Included RB tags > > > > v1 -> v2 > > * Dropped including makefile change > > * Updated ndev count > > --- > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > new file mode 100644 > > index 000000000000..50134be548f5 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > @@ -0,0 +1,57 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > + > > +#include <arm64/renesas/r9a07g043.dtsi> > The initial patch shouldn't be broken. Combine them together with the > minimal components and add others late. Don't separate the DTS files. > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two more patches [1] which are required and are currently queued up in the Renesas tree for v6.2 (Ive mentioned the dependencies in the cover letter). [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > + > > +/ { > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <12000000>; > > + > > + cpu0: cpu@0 { > > + compatible = "andestech,ax45mp", "riscv"; > > + device_type = "cpu"; > > + reg = <0x0>; > > + status = "okay"; > > + riscv,isa = "rv64imafdc"; > > + mmu-type = "riscv,sv39"; > > + i-cache-size = <0x8000>; > > + i-cache-line-size = <0x40>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <0x40>; > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > > + > > + cpu0_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + }; > > +}; > > + > > +&soc { > > + interrupt-parent = <&plic>; > > + > > + plic: interrupt-controller@12c00000 { > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > > + #interrupt-cells = <2>; > > + #address-cells = <0>; > > + riscv,ndev = <511>; > > + interrupt-controller; > > + reg = <0x0 0x12c00000 0 0x400000>; > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > Ditto, Where is cpg? in r9a07g043.dtsi? > Yes CPG node is in r9a07g043.dtsi. Cheers, Prabhakar
On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Guo, > > Thank you for the review. > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > Single). > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > - AX45MP CPU > > > - PLIC > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- > > > v4 -> v5 > > > * Fixed riscv,ndev value (should be 511) > > > * Reworked completely (sort of new patch) > > > > > > v3 -> v4 > > > * No change > > > > > > v2 -> v3 > > > * Fixed clock entry for CPU core > > > * Fixed timebase frequency to 12MHz > > > * Fixed sorting of the nodes > > > * Included RB tags > > > > > > v1 -> v2 > > > * Dropped including makefile change > > > * Updated ndev count > > > --- > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > 1 file changed, 57 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > new file mode 100644 > > > index 000000000000..50134be548f5 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > @@ -0,0 +1,57 @@ > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +/* > > > + * Device Tree Source for the RZ/Five SoC > > > + * > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > + */ > > > + > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > + > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > + > > > +#include <arm64/renesas/r9a07g043.dtsi> > > The initial patch shouldn't be broken. Combine them together with the > > minimal components and add others late. Don't separate the DTS files. > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > more patches [1] which are required and are currently queued up in the > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > letter). You could just move the below part to the second dtsi patch. Then compile won't be broken. clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > > > + > > > +/ { > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + timebase-frequency = <12000000>; > > > + > > > + cpu0: cpu@0 { > > > + compatible = "andestech,ax45mp", "riscv"; > > > + device_type = "cpu"; > > > + reg = <0x0>; > > > + status = "okay"; > > > + riscv,isa = "rv64imafdc"; > > > + mmu-type = "riscv,sv39"; > > > + i-cache-size = <0x8000>; > > > + i-cache-line-size = <0x40>; > > > + d-cache-size = <0x8000>; > > > + d-cache-line-size = <0x40>; > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > > > + > > > + cpu0_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + }; > > > +}; > > > + > > > +&soc { > > > + interrupt-parent = <&plic>; > > > + > > > + plic: interrupt-controller@12c00000 { > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > > > + #interrupt-cells = <2>; > > > + #address-cells = <0>; > > > + riscv,ndev = <511>; > > > + interrupt-controller; > > > + reg = <0x0 0x12c00000 0 0x400000>; > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > + power-domains = <&cpg>; > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > Ditto, Where is cpg? in r9a07g043.dtsi? > > > Yes CPG node is in r9a07g043.dtsi. > > Cheers, > Prabhakar -- Best Regards Guo Ren
On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > > > Hi Guo, > > > > Thank you for the review. > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > Single). > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > - AX45MP CPU > > > > - PLIC > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- > > > > v4 -> v5 > > > > * Fixed riscv,ndev value (should be 511) > > > > * Reworked completely (sort of new patch) > > > > > > > > v3 -> v4 > > > > * No change > > > > > > > > v2 -> v3 > > > > * Fixed clock entry for CPU core > > > > * Fixed timebase frequency to 12MHz > > > > * Fixed sorting of the nodes > > > > * Included RB tags > > > > > > > > v1 -> v2 > > > > * Dropped including makefile change > > > > * Updated ndev count > > > > --- > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > 1 file changed, 57 insertions(+) > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > new file mode 100644 > > > > index 000000000000..50134be548f5 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > @@ -0,0 +1,57 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +/* > > > > + * Device Tree Source for the RZ/Five SoC > > > > + * > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > + */ > > > > + > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > + > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > + > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > The initial patch shouldn't be broken. Combine them together with the > > > minimal components and add others late. Don't separate the DTS files. > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > more patches [1] which are required and are currently queued up in the > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > letter). > > You could just move the below part to the second dtsi patch. Then > compile won't be broken. > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > power-domains = <&cpg>; > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; The makefile for this directory is not added until the next patch right? The compile shouldn't be broken here since it therefore cannot be compiled? Slightly confused, Conor. > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > > > > > + > > > > +/ { > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + timebase-frequency = <12000000>; > > > > + > > > > + cpu0: cpu@0 { > > > > + compatible = "andestech,ax45mp", "riscv"; > > > > + device_type = "cpu"; > > > > + reg = <0x0>; > > > > + status = "okay"; > > > > + riscv,isa = "rv64imafdc"; > > > > + mmu-type = "riscv,sv39"; > > > > + i-cache-size = <0x8000>; > > > > + i-cache-line-size = <0x40>; > > > > + d-cache-size = <0x8000>; > > > > + d-cache-line-size = <0x40>; > > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > > > > + > > > > + cpu0_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + }; > > > > +}; > > > > + > > > > +&soc { > > > > + interrupt-parent = <&plic>; > > > > + > > > > + plic: interrupt-controller@12c00000 { > > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > > > > + #interrupt-cells = <2>; > > > > + #address-cells = <0>; > > > > + riscv,ndev = <511>; > > > > + interrupt-controller; > > > > + reg = <0x0 0x12c00000 0 0x400000>; > > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > > + power-domains = <&cpg>; > > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > Ditto, Where is cpg? in r9a07g043.dtsi? > > > > > Yes CPG node is in r9a07g043.dtsi. > > > > Cheers, > > Prabhakar > > > > -- > Best Regards > Guo Ren
Hi Guo, On Sun, Oct 30, 2022 at 1:02 AM Guo Ren <guoren@kernel.org> wrote: > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > > > Hi Guo, > > > > Thank you for the review. > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > Single). > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > - AX45MP CPU > > > > - PLIC > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- > > > > v4 -> v5 > > > > * Fixed riscv,ndev value (should be 511) > > > > * Reworked completely (sort of new patch) > > > > > > > > v3 -> v4 > > > > * No change > > > > > > > > v2 -> v3 > > > > * Fixed clock entry for CPU core > > > > * Fixed timebase frequency to 12MHz > > > > * Fixed sorting of the nodes > > > > * Included RB tags > > > > > > > > v1 -> v2 > > > > * Dropped including makefile change > > > > * Updated ndev count > > > > --- > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > 1 file changed, 57 insertions(+) > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > new file mode 100644 > > > > index 000000000000..50134be548f5 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > @@ -0,0 +1,57 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +/* > > > > + * Device Tree Source for the RZ/Five SoC > > > > + * > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > + */ > > > > + > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > + > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > + > > > > +#include <arm64/renesas/r9a07g043.dtsi> ^^^ look below... > > > The initial patch shouldn't be broken. Combine them together with the > > > minimal components and add others late. Don't separate the DTS files. > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > more patches [1] which are required and are currently queued up in the > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > letter). > > You could just move the below part to the second dtsi patch. Then > compile won't be broken. > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > power-domains = <&cpg>; > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > Compile won't break at all, the CPG node [0] and the pinctrl node [1] already exists in the kernel which is being re-used by this SoC DTSI. ... the include file above already exists in the kernel and is not part of the next follow up patch. [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n541 [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563 Cheers, Prabhakar
Hi Conor, On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote: > > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > > > > Hi Guo, > > > > > > Thank you for the review. > > > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > > Single). > > > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > - AX45MP CPU > > > > > - PLIC > > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- > > > > > v4 -> v5 > > > > > * Fixed riscv,ndev value (should be 511) > > > > > * Reworked completely (sort of new patch) > > > > > > > > > > v3 -> v4 > > > > > * No change > > > > > > > > > > v2 -> v3 > > > > > * Fixed clock entry for CPU core > > > > > * Fixed timebase frequency to 12MHz > > > > > * Fixed sorting of the nodes > > > > > * Included RB tags > > > > > > > > > > v1 -> v2 > > > > > * Dropped including makefile change > > > > > * Updated ndev count > > > > > --- > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > > 1 file changed, 57 insertions(+) > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > new file mode 100644 > > > > > index 000000000000..50134be548f5 > > > > > --- /dev/null > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > @@ -0,0 +1,57 @@ > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > +/* > > > > > + * Device Tree Source for the RZ/Five SoC > > > > > + * > > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > > + */ > > > > > + > > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > > + > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > > + > > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > > The initial patch shouldn't be broken. Combine them together with the > > > > minimal components and add others late. Don't separate the DTS files. > > > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > > more patches [1] which are required and are currently queued up in the > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > > letter). > > > > You could just move the below part to the second dtsi patch. Then > > compile won't be broken. > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > power-domains = <&cpg>; > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > The makefile for this directory is not added until the next patch right? > The compile shouldn't be broken here since it therefore cannot be > compiled? > These nodes are already present in the kernel [0] so the makefile change in the next patch if made here still won't break the compilation alone of SoC DTSI (included in dts). [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563 Cheers, Prabhakar
On Sun, Oct 30, 2022 at 10:27:17PM +0000, Lad, Prabhakar wrote: > Hi Conor, > > > You could just move the below part to the second dtsi patch. Then > > > compile won't be broken. > > > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > power-domains = <&cpg>; > > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > > The makefile for this directory is not added until the next patch right? > > The compile shouldn't be broken here since it therefore cannot be > > compiled? > > > These nodes are already present in the kernel [0] so the makefile > change in the next patch if made here still won't break the > compilation alone of SoC DTSI (included in dts). Yeah I know, I did actually build the dtb ;) I was just confused as to how Guo Ren had found a build issue with this patch that the follow on patch would fix, when this dtsi is not buildable in this patch.
On Mon, Oct 31, 2022 at 2:16 AM Conor Dooley <conor@kernel.org> wrote: > > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > > > > Hi Guo, > > > > > > Thank you for the review. > > > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > > Single). > > > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > - AX45MP CPU > > > > > - PLIC > > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- > > > > > v4 -> v5 > > > > > * Fixed riscv,ndev value (should be 511) > > > > > * Reworked completely (sort of new patch) > > > > > > > > > > v3 -> v4 > > > > > * No change > > > > > > > > > > v2 -> v3 > > > > > * Fixed clock entry for CPU core > > > > > * Fixed timebase frequency to 12MHz > > > > > * Fixed sorting of the nodes > > > > > * Included RB tags > > > > > > > > > > v1 -> v2 > > > > > * Dropped including makefile change > > > > > * Updated ndev count > > > > > --- > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > > 1 file changed, 57 insertions(+) > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > new file mode 100644 > > > > > index 000000000000..50134be548f5 > > > > > --- /dev/null > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > @@ -0,0 +1,57 @@ > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > +/* > > > > > + * Device Tree Source for the RZ/Five SoC > > > > > + * > > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > > + */ > > > > > + > > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > > + > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > > + > > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > > The initial patch shouldn't be broken. Combine them together with the > > > > minimal components and add others late. Don't separate the DTS files. > > > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > > more patches [1] which are required and are currently queued up in the > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > > letter). > > > > You could just move the below part to the second dtsi patch. Then > > compile won't be broken. > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > power-domains = <&cpg>; > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > The makefile for this directory is not added until the next patch right? > The compile shouldn't be broken here since it therefore cannot be > compiled? If you put a DTS without a makefile added, it's an unused code in the repo. I still prefer to add them one by one and ensure every patch could be properly compiled. This patch series unnecessarily broke the compilation of the first patches. > > Slightly confused, > Conor. > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > > > > > > > + > > > > > +/ { > > > > > + cpus { > > > > > + #address-cells = <1>; > > > > > + #size-cells = <0>; > > > > > + timebase-frequency = <12000000>; > > > > > + > > > > > + cpu0: cpu@0 { > > > > > + compatible = "andestech,ax45mp", "riscv"; > > > > > + device_type = "cpu"; > > > > > + reg = <0x0>; > > > > > + status = "okay"; > > > > > + riscv,isa = "rv64imafdc"; > > > > > + mmu-type = "riscv,sv39"; > > > > > + i-cache-size = <0x8000>; > > > > > + i-cache-line-size = <0x40>; > > > > > + d-cache-size = <0x8000>; > > > > > + d-cache-line-size = <0x40>; > > > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > > > > > + > > > > > + cpu0_intc: interrupt-controller { > > > > > + #interrupt-cells = <1>; > > > > > + compatible = "riscv,cpu-intc"; > > > > > + interrupt-controller; > > > > > + }; > > > > > + }; > > > > > + }; > > > > > +}; > > > > > + > > > > > +&soc { > > > > > + interrupt-parent = <&plic>; > > > > > + > > > > > + plic: interrupt-controller@12c00000 { > > > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > > > > > + #interrupt-cells = <2>; > > > > > + #address-cells = <0>; > > > > > + riscv,ndev = <511>; > > > > > + interrupt-controller; > > > > > + reg = <0x0 0x12c00000 0 0x400000>; > > > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > > > + power-domains = <&cpg>; > > > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > > Ditto, Where is cpg? in r9a07g043.dtsi? > > > > > > > Yes CPG node is in r9a07g043.dtsi. > > > > > > Cheers, > > > Prabhakar > > > > > > > > -- > > Best Regards > > Guo Ren
On Mon, Oct 31, 2022 at 6:27 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Conor, > > On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > > > <prabhakar.csengg@gmail.com> wrote: > > > > > > > > Hi Guo, > > > > > > > > Thank you for the review. > > > > > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > > > Single). > > > > > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > > - AX45MP CPU > > > > > > - PLIC > > > > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > --- > > > > > > v4 -> v5 > > > > > > * Fixed riscv,ndev value (should be 511) > > > > > > * Reworked completely (sort of new patch) > > > > > > > > > > > > v3 -> v4 > > > > > > * No change > > > > > > > > > > > > v2 -> v3 > > > > > > * Fixed clock entry for CPU core > > > > > > * Fixed timebase frequency to 12MHz > > > > > > * Fixed sorting of the nodes > > > > > > * Included RB tags > > > > > > > > > > > > v1 -> v2 > > > > > > * Dropped including makefile change > > > > > > * Updated ndev count > > > > > > --- > > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > > > 1 file changed, 57 insertions(+) > > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > new file mode 100644 > > > > > > index 000000000000..50134be548f5 > > > > > > --- /dev/null > > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > @@ -0,0 +1,57 @@ > > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > +/* > > > > > > + * Device Tree Source for the RZ/Five SoC > > > > > > + * > > > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > > > + */ > > > > > > + > > > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > > > + > > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > > > + > > > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > > > The initial patch shouldn't be broken. Combine them together with the > > > > > minimal components and add others late. Don't separate the DTS files. > > > > > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > > > more patches [1] which are required and are currently queued up in the > > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > > > letter). > > > > > > You could just move the below part to the second dtsi patch. Then > > > compile won't be broken. > > > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > power-domains = <&cpg>; > > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > > The makefile for this directory is not added until the next patch right? > > The compile shouldn't be broken here since it therefore cannot be > > compiled? > > > These nodes are already present in the kernel [0] so the makefile > change in the next patch if made here still won't break the > compilation alone of SoC DTSI (included in dts). Oh... Sorry, I screwed up. The arch/arm64/boot/dts/renesas/r9a07g043.dtsi is not belonged to the patch series. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563 > > Cheers, > Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > Single). > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > can be used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - PLIC > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v4 -> v5 > * Fixed riscv,ndev value (should be 511) > * Reworked completely (sort of new patch) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi new file mode 100644 index 000000000000..50134be548f5 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) + +#include <arm64/renesas/r9a07g043.dtsi> + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <12000000>; + + cpu0: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; +}; + +&soc { + interrupt-parent = <&plic>; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <511>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; +};