From patchwork Thu Nov 3 07:50:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13029663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E83DC433FE for ; Thu, 3 Nov 2022 07:52:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MljyLFrwoYpUnBKWmCXyiL22zBzFar/KyKcUsQSEWgE=; b=Ljnic5xhLwcj3R cj7ub97Haf+ZDa4+/oKwvva7LxfVi1xtNYjuDnEKMSFSdEfDiRhFwZoAzw23gDVkQUDcSQwJRymYH rv9uFTtPs/MRbyNENQLc/9MAcnRWTnyrlgOWbjI8q6cc3CVS2YUWICg1vqPBH9bbH5CU7/H95o1Kw I5zalobvg/Ke+jpu7EvKWRA2fZeqE1qlBBnufKosjR36D9MaHsjBumEE7cqKhoEXlb84OwfRD6g/t N+rRFBQCKz8vxIGCJL8wEs0trhmEazoviXBmGPZ6lMyKJp1D0lDsgQI8Xf8+4SGm8cnNH3Of5aPAr menHl8dul7+eMpavoB/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqV1b-00GW9B-Px; Thu, 03 Nov 2022 07:52:31 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqV1Y-00GW6f-7q for linux-riscv@lists.infradead.org; Thu, 03 Nov 2022 07:52:29 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CE47061D85; Thu, 3 Nov 2022 07:52:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4473FC433B5; Thu, 3 Nov 2022 07:52:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667461947; bh=0K2hv/sIizd7ky6ouBl81veZ36d3hA0AYFyvgZS3ciY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tCITk7V8W/fqya7h7EU4wMXFagRpx8Ck6z7+nm7uTCSD6GoEvvNTStoQaGvDxADNK OjODZttEb0iS2G1Lpjalryw1Xwn/1hGgf/8THv/b5pzg3+GWUBi8smp0kEYd0ioIne Q6gv8GAsgAYDTVX45/O4hOW8q2X+ScnZ4wtnsyB7MDu9G0cDXa+YzbT9JoJRWK36H+ kR0NEscwaZA6eUB1Oo9yy2vtgowZ1cemjM77IvDFEj22XUJl37nccMsSLJhfWLwu3l cbb2WCPf+8qGdfwMlqiYcsKUKH2kti4ilOvBJey/VdYCxhAq9R7+gUqIT7j4xL2vbD qVFSuxAfwP2+Q== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, palmer@dabbelt.com, paul.walmsley@sifive.com, mark.rutland@arm.com, zouyipeng@huawei.com, bigeasy@linutronix.de, David.Laight@aculab.com, chenzhongjin@huawei.com, greentime.hu@sifive.com, andy.chiu@sifive.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH -next V8 08/14] riscv: Support HAVE_SOFTIRQ_ON_OWN_STACK Date: Thu, 3 Nov 2022 03:50:41 -0400 Message-Id: <20221103075047.1634923-9-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221103075047.1634923-1-guoren@kernel.org> References: <20221103075047.1634923-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_005228_381208_7E5EB51A X-CRM114-Status: GOOD ( 14.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Add the HAVE_SOFTIRQ_ON_OWN_STACK feature for the IRQ_STACKS config. The irq and softirq use the same independent irq_stack of percpu by time division multiplexing. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Sebastian Andrzej Siewior --- arch/riscv/Kconfig | 7 ++++--- arch/riscv/kernel/irq.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2653a381cc62..85241415a935 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -446,12 +446,13 @@ config FPU If you don't know what to do here, say Y. config IRQ_STACKS - bool "Independent irq stacks" if EXPERT + bool "Independent irq & softirq stacks" if EXPERT default y select HAVE_IRQ_EXIT_ON_IRQ_STACK + select HAVE_SOFTIRQ_ON_OWN_STACK help - Add independent irq stacks for percpu to prevent kernel stack overflows. - We may save some memory footprint by disabling IRQ_STACKS. + Add independent irq & softirq stacks for percpu to prevent kernel stack + overflows. We may save some memory footprint by disabling IRQ_STACKS. endmenu # "Platform type" diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 5d77f692b198..a6406da34937 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #ifdef CONFIG_IRQ_STACKS static DEFINE_PER_CPU(ulong *, irq_stack_ptr); @@ -38,6 +39,38 @@ static void init_irq_stacks(void) per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu); } #endif /* CONFIG_VMAP_STACK */ + +#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK +void do_softirq_own_stack(void) +{ +#ifdef CONFIG_IRQ_STACKS + if (on_thread_stack()) { + ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id()) + + IRQ_STACK_SIZE/sizeof(ulong); + __asm__ __volatile( + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" ra, (sp) \n" + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" s0, (sp) \n" + "addi s0, sp, 2*"RISCV_SZPTR "\n" + "move sp, %[sp] \n" + "call __do_softirq \n" + "addi sp, s0, -2*"RISCV_SZPTR"\n" + REG_L" s0, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + REG_L" ra, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + : + : [sp] "r" (sp) + : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "memory"); + } else +#endif + __do_softirq(); +} +#endif /* CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK */ + #else static void init_irq_stacks(void) {} #endif /* CONFIG_IRQ_STACKS */