| Message ID | 20221118010627.70576-15-hal.feng@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Basic clock and reset support for StarFive JH7110 RISC-V SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/patch_count | success | Link |
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/build_warn_rv64 | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 21 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@starfivetech.com> wrote: > > The JH7110 clock drivers will not register redundant auxiliary > devices if the JH7110 reset auxiliary driver is disabled. > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c > index dda19c6937cb..4e69f56b00cc 100644 > --- a/drivers/clk/starfive/clk-starfive-jh71x0.c > +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c > @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) > } > EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); > > -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) > +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) I don't see any reason you'd want to build a kernel that needs the clock driver but not the resets, so I don't think this is something we should optimize for. I'd just drop this patch and let such broken kernels register the auxiliary devices even when no reset driver is there to use them. > static void jh7110_reset_unregister_adev(void *_adev) > { > @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, > } > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); > > +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ > + > +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, > + const char *adev_name, > + u32 adev_id) > +{ > + return 0; > +} > + > #endif > -- > 2.38.1 >
On Sat, 19 Nov 2022 01:18:18 +0800, Emil Renner Berthing wrote: > On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@starfivetech.com> wrote: >> >> The JH7110 clock drivers will not register redundant auxiliary >> devices if the JH7110 reset auxiliary driver is disabled. >> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++- >> 1 file changed, 10 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c >> index dda19c6937cb..4e69f56b00cc 100644 >> --- a/drivers/clk/starfive/clk-starfive-jh71x0.c >> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c >> @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) >> } >> EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); >> >> -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) >> +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) > > I don't see any reason you'd want to build a kernel that needs the > clock driver but not the resets, so I don't think this is something we > should optimize for. I'd just drop this patch and let such broken > kernels register the auxiliary devices even when no reset driver is > there to use them. You're right. I made this patch just following the style of jh7100. And I think it's better to select RESET_STARFIVE_JH7110 in config CLK_STARFIVE_JH7110_SYS. Best regards, Hal > >> static void jh7110_reset_unregister_adev(void *_adev) >> { >> @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, >> } >> EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); >> >> +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ >> + >> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, >> + const char *adev_name, >> + u32 adev_id) >> +{ >> + return 0; >> +} >> + >> #endif
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c index dda19c6937cb..4e69f56b00cc 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) } EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) static void jh7110_reset_unregister_adev(void *_adev) { @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, } EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ + +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, + const char *adev_name, + u32 adev_id) +{ + return 0; +} + #endif
The JH7110 clock drivers will not register redundant auxiliary devices if the JH7110 reset auxiliary driver is disabled. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)