| Message ID | 20221120082114.3030-5-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: add Bouffalolab bl808 support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
On Sun, Nov 20, 2022 at 04:21:11PM +0800, Jisheng Zhang wrote: > The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and > LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Could you also add this new SOC_BOUFFALOLAB symbol to defconfig please? > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..90256f44ed4a 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,11 @@ > menu "SoC selection" > > +config SOC_BOUFFALOLAB > + bool "Bouffalolab SoCs" > + select SIFIVE_PLIC > + help > + This enables support for Bouffalolab SoC platforms. > + > config SOC_MICROCHIP_POLARFIRE > bool "Microchip PolarFire SoCs" > select MCHP_CLK_MPFS > -- > 2.37.2 >
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..90256f44ed4a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config SOC_BOUFFALOLAB + bool "Bouffalolab SoCs" + select SIFIVE_PLIC + help + This enables support for Bouffalolab SoC platforms. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS
The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+)