| Message ID | 20221127132448.4034-4-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: add Bouffalolab bl808 support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
On 11/27/22 07:24, Jisheng Zhang wrote: > The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and > LP. The D0 is 64bit RISC-V GC compatible, so can run linux. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..90256f44ed4a 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,11 @@ > menu "SoC selection" > > +config SOC_BOUFFALOLAB The options in this file are getting renamed soon, so this should be named ARCH_BOUFFALOLAB. See https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ Regards, Samuel > + bool "Bouffalolab SoCs" > + select SIFIVE_PLIC > + help > + This enables support for Bouffalolab SoC platforms. > + > config SOC_MICROCHIP_POLARFIRE > bool "Microchip PolarFire SoCs" > select MCHP_CLK_MPFS
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..90256f44ed4a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config SOC_BOUFFALOLAB + bool "Bouffalolab SoCs" + select SIFIVE_PLIC + help + This enables support for Bouffalolab SoC platforms. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS