| Message ID | 20221127132448.4034-7-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | riscv: add Bouffalolab bl808 support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
+CC Icenowy On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..f4b170ccc32e > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; Hmm, @Icenowy - should this use your new open-c906-plic compatible from 20221121041757.418645-4-uwu@icenowy.me ? As is, dtbs_check gives a: bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: 'oneOf' conditional failed, one must be fixed: ['thead,c900-plic'] is too short > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; > + }; > + }; > +}; > -- > 2.38.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
在 2022-11-27星期日的 17:21 +0000，Conor Dooley写道： > +CC Icenowy > > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 1 file changed, 74 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..f4b170ccc32e > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > + compatible = "bouffalolab,bl808-uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; > > Hmm, @Icenowy - should this use your new open-c906-plic compatible > from > 20221121041757.418645-4-uwu@icenowy.me ? I am against using openc906-plic. Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid compatible, as there seems to be few options related to PLIC/CLINT for C906/C910 (at least as the open document of them say). > > As is, dtbs_check gives a: > bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: > 'oneOf' conditional failed, one must be fixed: > ['thead,c900-plic'] is too short > > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > + }; > > + }; > > +}; > > -- > > 2.38.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, Nov 28, 2022 at 05:52:51PM +0800, Icenowy Zheng wrote: > 在 2022-11-27星期日的 17:21 +0000，Conor Dooley写道： > > +CC Icenowy > > > > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > > Hmm, @Icenowy - should this use your new open-c906-plic compatible > > from > > 20221121041757.418645-4-uwu@icenowy.me ? > > I am against using openc906-plic. > > Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid > compatible, as there seems to be few options related to PLIC/CLINT for > C906/C910 (at least as the open document of them say). You two know this a lot better than I do, I'll leave it up to you two to sort out :) Either way, we need something changed here to satisfy the bindings. > > As is, dtbs_check gives a: > > bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: > > 'oneOf' conditional failed, one must be fixed: > > ['thead,c900-plic'] is too short > > > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > + }; > > > + }; > > > +};
On 11/27/22 07:24, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..f4b170ccc32e > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { It's unfortunate that the SDK/documentation calls this peripheral both UART0 and UART3. I don't know if we can/should put the "M0" and "D0" bus peripherals in the same DT; it seems like most of the "M0" peripherals are not accessible from the C906. But if we did, this would conflict with the other UART0. > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; There's a clock controller with a mux and a gate between the crystal and the UART. I'm not sure what the policy is about adding "fake" suppliers before the real supplier has a binding defined. Unfortunately, Bouffalolab threw everything and the kitchen sink into the GLB register space, so that complicates defining the binding for the clock/reset controller part. > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, The C906 PLIC has an M-mode context, so 0xffffffff is not correct. This should reference the M-mode external interrupt. > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so this value should be at least that. Regards, Samuel > + }; > + }; > +};
在 2022-11-30星期三的 01:21 -0600，Samuel Holland写道： > On 11/27/22 07:24, Jisheng Zhang wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 1 file changed, 74 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..f4b170ccc32e > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > It's unfortunate that the SDK/documentation calls this peripheral > both > UART0 and UART3. I don't know if we can/should put the "M0" and "D0" > bus > peripherals in the same DT; it seems like most of the "M0" > peripherals > are not accessible from the C906. But if we did, this would conflict > with the other UART0. They're accessible but their interrupts are not, and I think this is called d0_uart or uart3, but not uart0 at all. > > > + compatible = "bouffalolab,bl808-uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > There's a clock controller with a mux and a gate between the crystal > and > the UART. I'm not sure what the policy is about adding "fake" > suppliers > before the real supplier has a binding defined. > > Unfortunately, Bouffalolab threw everything and the kitchen sink into > the GLB register space, so that complicates defining the binding for > the > clock/reset controller part. > > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; Using a single c900-plic here needs more discussion, I think. > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > The C906 PLIC has an M-mode context, so 0xffffffff is not correct. > This > should reference the M-mode external interrupt. > > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so > this value should be at least that. > > Regards, > Samuel > > > + }; > > + }; > > +}; > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, Dec 05, 2022 at 04:17:59PM +0800, Icenowy Zheng wrote: > 在 2022-11-30星期三的 01:21 -0600，Samuel Holland写道： > > On 11/27/22 07:24, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > ++++++++++++++++++++++ > > > 1 file changed, 74 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > new file mode 100644 > > > index 000000000000..f4b170ccc32e > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > @@ -0,0 +1,74 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > > +/* > > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > > + */ > > > + > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > + > > > +/ { > > > + compatible = "bouffalolab,bl808"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + cpus { > > > + timebase-frequency = <1000000>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + compatible = "thead,c906", "riscv"; > > > + device_type = "cpu"; > > > + reg = <0>; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <256>; > > > + d-cache-size = <32768>; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <128>; > > > + i-cache-size = <32768>; > > > + mmu-type = "riscv,sv39"; > > > + riscv,isa = "rv64imafdc"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + xtal: xtal-clk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + /* This value must be overridden by the board */ > > > + clock-frequency = <0>; > > > + }; > > > + > > > + soc { > > > + compatible = "simple-bus"; > > > + ranges; > > > + interrupt-parent = <&plic>; > > > + dma-noncoherent; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + uart0: serial@30002000 { > > > > It's unfortunate that the SDK/documentation calls this peripheral > > both > > UART0 and UART3. I don't know if we can/should put the "M0" and "D0" > > bus > > peripherals in the same DT; it seems like most of the "M0" > > peripherals > > are not accessible from the C906. But if we did, this would conflict > > with the other UART0. > > They're accessible but their interrupts are not, and I think this is > called d0_uart or uart3, but not uart0 at all. > > > > > > + compatible = "bouffalolab,bl808-uart"; > > > + reg = <0x30002000 0x1000>; > > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&xtal>; > > > > There's a clock controller with a mux and a gate between the crystal > > and the UART. I'm not sure what the policy is about adding "fake" > > suppliers before the real supplier has a binding defined. > > > > Unfortunately, Bouffalolab threw everything and the kitchen sink into > > the GLB register space, so that complicates defining the binding for > > the clock/reset controller part. I think it depends on how backwards/forwards compatible it's going to be? If new kernel + old DT works then that's all that's "required", right? Old kernel + new DT isn't going to work, but that's not required AFAIU. > > > > > + status = "disabled"; > > > + }; > > > + > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > Using a single c900-plic here needs more discussion, I think. Yah. Per the discussion on [1], I think I'd rather we avoided the single c900-plic. Either a SoC-specific value, or "something" involving the "openplic" naming is needed here. Thanks, Conor. 1 - https://lore.kernel.org/linux-riscv/20221121041757.418645-3-uwu@icenowy.me/ > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > > The C906 PLIC has an M-mode context, so 0xffffffff is not correct. > > This > > should reference the M-mode external interrupt. > > > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > > The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so > > this value should be at least that. > > > > Regards, > > Samuel > > > > > + }; > > > + }; > > > +};
Hi, > + uart0: serial@30002000 { According to the reference manual of the bl808, this is uart3. Can we also use that name here? > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; This is a shortcut and is likely to change in the future. The xtal isn't really connected to the uart block, but instead there is a clock mux and clock gate in between. > + status = "disabled"; > + }; Thanks, -michael
diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 000000000000..f4b170ccc32e --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@30002000 { + compatible = "bouffalolab,bl808-uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <64>; + }; + }; +};
Add a baisc dtsi for the bouffalolab bl808 SoC. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi