| Message ID | 20221216070632.11444-10-yanhong.wang@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Ethernet driver for StarFive JH7110 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Guessing tree name failed |
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts index c8946cf3a268..81329d67ef0f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts @@ -15,6 +15,8 @@ aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -114,3 +116,29 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&gmac0 { + status = "okay"; +}; + +&phy0 { + rxc_dly_en = <1>; + tx_delay_sel_fe = <5>; + tx_delay_sel = <0xa>; + tx_inverted_10 = <0x1>; + tx_inverted_100 = <0x1>; + tx_inverted_1000 = <0x1>; +}; + +&gmac1 { + status = "okay"; +}; + +&phy1 { + rxc_dly_en = <0>; + tx_delay_sel_fe = <5>; + tx_delay_sel = <0>; + tx_inverted_10 = <0x1>; + tx_inverted_100 = <0x1>; + tx_inverted_1000 = <0x0>; +};
In view of the particularity of StarFive JH7110 SoC, the PHY clock delay train configuration parameters must be adjusted for StarFive VisionFive v2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> --- .../jh7110-starfive-visionfive-v2.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+)