| Message ID | 20230103062610.69704-2-uwu@icenowy.me (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [RESEND,1/2] riscv: errata: fix T-Head dcache.cva encoding | expand |
On Tue, Jan 03, 2023 at 10:18:49AM +0000, Conor Dooley wrote: > > T-Head now maintains some specification for their extended instructions > > at [1], in which all instructions are prefixed "th.". > > > > Follow this practice in the kernel comments. > > > > [1] https://github.com/T-head-Semi/thead-extension-spec > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > Hey Icenowy, > This (yet again) appears to not have made it to the list. > It's not on patchwork, nor lore: > https://lore.kernel.org/linux-riscv/2668919.mvXUDI8C0e@diego/T/#t > https://lore.kernel.org/all/2668919.mvXUDI8C0e@diego/T/#t > > Since you CCed lkml & not just linux-riscv, but it is not showing idk > what's wrong.. > Your reply to me the other day came through: > https://lore.kernel.org/all/dda144a8397a175f3ce092485f08896c9a66d232.camel@icenowy.me/ This (and the previous iteration) finally came through to the list. I guess the pusher-of-buttons for "suspicious" mail or w/e is back to work after Christmas. It's in patchwork now: https://patchwork.kernel.org/project/linux-riscv/list/?series=708586 Thanks, Conor.
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 605800bd390e..46adc1c9428f 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -92,25 +92,25 @@ asm volatile(ALTERNATIVE( \ #endif /* - * dcache.ipa rs1 (invalidate, physical address) + * th.dcache.ipa rs1 (invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01010 rs1 000 00000 0001011 - * dache.iva rs1 (invalida, virtual address) + * th.dcache.iva rs1 (invalida, virtual address) * 0000001 00110 rs1 000 00000 0001011 * - * dcache.cpa rs1 (clean, physical address) + * th.dcache.cpa rs1 (clean, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01001 rs1 000 00000 0001011 - * dcache.cva rs1 (clean, virtual address) + * th.dcache.cva rs1 (clean, virtual address) * 0000001 00101 rs1 000 00000 0001011 * - * dcache.cipa rs1 (clean then invalidate, physical address) + * th.dcache.cipa rs1 (clean then invalidate, physical address) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000001 01011 rs1 000 00000 0001011 - * dcache.civa rs1 (... virtual address) + * th.dcache.civa rs1 (... virtual address) * 0000001 00111 rs1 000 00000 0001011 * - * sync.s (make sure all cache operations finished) + * th.sync.s (make sure all cache operations finished) * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */
T-Head now maintains some specification for their extended instructions at [1], in which all instructions are prefixed "th.". Follow this practice in the kernel comments. [1] https://github.com/T-head-Semi/thead-extension-spec Signed-off-by: Icenowy Zheng <uwu@icenowy.me> --- arch/riscv/include/asm/errata_list.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)