diff mbox series

[v5,3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2

Message ID 20230117015445.32500-4-jiajie.ho@starfivetech.com (mailing list archive)
State Handled Elsewhere
Delegated to: Conor Dooley
Headers show
Series hwrng: starfive: Add driver for TRNG module | expand

Checks

Context Check Description
conchuod/tree_selection fail Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Jia Jie Ho Jan. 17, 2023, 1:54 a.m. UTC 
Adding StarFive TRNG controller node to VisionFive 2 SoC.

Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Palmer Dabbelt March 15, 2023, 1:45 a.m. UTC | #1 
On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
> Adding StarFive TRNG controller node to VisionFive 2 SoC.
>
> Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 4ac159d79d66..3c29e0bc6246 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -455,5 +455,15 @@ uart5: serial@12020000 {
>  			reg-shift = <2>;
>  			status = "disabled";
>  		};
> +
> +		rng: rng@1600c000 {
> +			compatible = "starfive,jh7110-trng";
> +			reg = <0x0 0x1600C000 0x0 0x4000>;
> +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> +			clock-names = "hclk", "ahb";
> +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> +			interrupts = <30>;
> +		};
>  	};
>  };

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Aurelien Jarno July 1, 2023, 9:53 p.m. UTC | #2 
On 2023-03-14 18:45, Palmer Dabbelt wrote:
> On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
> > Adding StarFive TRNG controller node to VisionFive 2 SoC.
> > 
> > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
> > ---
> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 4ac159d79d66..3c29e0bc6246 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
> >  			reg-shift = <2>;
> >  			status = "disabled";
> >  		};
> > +
> > +		rng: rng@1600c000 {
> > +			compatible = "starfive,jh7110-trng";
> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > +			clock-names = "hclk", "ahb";
> > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> > +			interrupts = <30>;
> > +		};
> >  	};
> >  };
> 
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

It appears that this patch has never been applied, although the rest of
the series has already been merged. Unfortunately it doesn't apply
anymore due to other changes to that file.

Could you please rebase and resend it?
Conor Dooley July 1, 2023, 11:05 p.m. UTC | #3 
On Sat, Jul 01, 2023 at 11:53:34PM +0200, Aurelien Jarno wrote:
> On 2023-03-14 18:45, Palmer Dabbelt wrote:
> > On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
> > > Adding StarFive TRNG controller node to VisionFive 2 SoC.
> > > 
> > > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> > > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
> > > ---
> > >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > index 4ac159d79d66..3c29e0bc6246 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
> > >  			reg-shift = <2>;
> > >  			status = "disabled";
> > >  		};
> > > +
> > > +		rng: rng@1600c000 {
> > > +			compatible = "starfive,jh7110-trng";
> > > +			reg = <0x0 0x1600C000 0x0 0x4000>;
> > > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > > +			clock-names = "hclk", "ahb";
> > > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> > > +			interrupts = <30>;
> > > +		};
> > >  	};
> > >  };
> > 
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> It appears that this patch has never been applied, although the rest of
> the series has already been merged.

Ditto here, depends on the stgcrg, so it can't be applied yet.

> Unfortunately it doesn't apply
> anymore due to other changes to that file.
> 
> Could you please rebase and resend it?

No harm in a resend of course, given it doesn't apply.

Cheers,
Conor.
Jia Jie Ho July 3, 2023, 7:52 a.m. UTC | #4 
On 2/7/2023 5:53 am, Aurelien Jarno wrote:
> On 2023-03-14 18:45, Palmer Dabbelt wrote:
>> On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
>> > Adding StarFive TRNG controller node to VisionFive 2 SoC.
>> > 
>> > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
>> > ---
>> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>> >  1 file changed, 10 insertions(+)
>> > 
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 4ac159d79d66..3c29e0bc6246 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
>> >  			reg-shift = <2>;
>> >  			status = "disabled";
>> >  		};
>> > +
>> > +		rng: rng@1600c000 {
>> > +			compatible = "starfive,jh7110-trng";
>> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
>> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
>> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
>> > +			clock-names = "hclk", "ahb";
>> > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
>> > +			interrupts = <30>;
>> > +		};
>> >  	};
>> >  };
>> 
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> It appears that this patch has never been applied, although the rest of
> the series has already been merged. Unfortunately it doesn't apply
> anymore due to other changes to that file.
> 
> Could you please rebase and resend it?
> 

Hi Aurelien,

This patch is dependent on
https://patchwork.kernel.org/project/linux-riscv/patch/20230518101234.143748-2-xingyu.wu@starfivetech.com/

I'll send a new patch for this dts node after all dependencies have been merged.

Thanks,
Jia Jie
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4ac159d79d66..3c29e0bc6246 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -455,5 +455,15 @@  uart5: serial@12020000 {
 			reg-shift = <2>;
 			status = "disabled";
 		};
+
+		rng: rng@1600c000 {
+			compatible = "starfive,jh7110-trng";
+			reg = <0x0 0x1600C000 0x0 0x4000>;
+			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+			clock-names = "hclk", "ahb";
+			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+			interrupts = <30>;
+		};
 	};
 };