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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet Subject: [PATCH 02/24] ACPICA: MADT: Add RISC-V INTC interrupt controller Date: Mon, 30 Jan 2023 23:52:03 +0530 Message-Id: <20230130182225.2471414-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230130182225.2471414-1-sunilvl@ventanamicro.com> References: <20230130182225.2471414-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_102253_339223_78B5D63F X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , linux-doc@vger.kernel.org, Atish Patra , linux-kernel@vger.kernel.org, Robert Moore , linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org, acpica-devel@lists.linuxfoundation.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The ECR to add RISC-V INTC interrupt controller is approved by the UEFI forum and will be availabl in the next revision of the ACPI specification. This patch is not yet merged in ACPICA but a PR is raised. ACPICA PR: https://github.com/acpica/acpica/pull/804 Reference: Mantis ID: 2348 Cc: Robert Moore Cc: acpica-devel@lists.linuxfoundation.org Signed-off-by: Sunil V L --- include/acpi/actbl2.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index b2973dbe37ee..c432fd15db65 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -891,7 +891,8 @@ enum acpi_madt_type { ACPI_MADT_TYPE_MSI_PIC = 21, ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, - ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */ + ACPI_MADT_TYPE_RINTC = 24, + ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1250,6 +1251,24 @@ enum acpi_madt_lpc_pic_version { ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 24: RISC-V INTC */ +struct acpi_madt_rintc { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u64 hart_id; + u32 uid; /* ACPI processor UID */ +}; + +/* Values for RISC-V INTC Version field above */ + +enum acpi_madt_rintc_version { + ACPI_MADT_RINTC_VERSION_NONE = 0, + ACPI_MADT_RINTC_VERSION_V1 = 1, + ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ +}; + /* 80: OEM data */ struct acpi_madt_oem_data {