| Message ID | 20230209123636.123537-1-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | dac8bf14bb49aecd1de99ebb5498fa03152f2d40 |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: hwcap: Don't alphabetize ISA extension IDs | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 2471 this patch: 2471 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 17343 this patch: 17343 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 59 and now 59 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 2 this patch: 2 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 49 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, Feb 09, 2023 at 01:36:36PM +0100, Andrew Jones wrote: > While the comment above the ISA extension ID definitions says > "Entries are sorted alphabetically.", this stopped being good > advice with commit d8a3d8a75206 ("riscv: hwcap: make ISA extension > ids can be used in asm"), as we now use macros instead of enums. Yes, this ideally would have been removed by the commit doing the swap over, but as both were in-flight simultaneously it was missed. I intended going looking to see if this was dangling but clearly forgot. > Reshuffling defines is error-prone, so, since they don't need to be > in any particular order, change the advice to just adding new > extensions at the bottom. This aligns with what we "agreed" on Jisheng's patchset was the sanest way to handle this. > Also, take the opportunity to change > spaces to tabs, merge three comments into one, and move the base > and max defines into more logical locations wrt the ID definitions. Sure, why not... > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks for fixing this up Drew!
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 9 Feb 2023 13:36:36 +0100 you wrote: > While the comment above the ISA extension ID definitions says > "Entries are sorted alphabetically.", this stopped being good > advice with commit d8a3d8a75206 ("riscv: hwcap: make ISA extension > ids can be used in asm"), as we now use macros instead of enums. > Reshuffling defines is error-prone, so, since they don't need to be > in any particular order, change the advice to just adding new > extensions at the bottom. Also, take the opportunity to change > spaces to tabs, merge three comments into one, and move the base > and max defines into more logical locations wrt the ID definitions. > > [...] Here is the summary with links: - riscv: hwcap: Don't alphabetize ISA extension IDs https://git.kernel.org/riscv/c/dac8bf14bb49 You are awesome, thank you!
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index ee9c80fe0062..2a6dac9434b3 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -24,29 +24,27 @@ #define RISCV_ISA_EXT_u ('u' - 'a') /* - * Increse this to higher value as kernel support more ISA extensions. - */ -#define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 - -/* The base ID for multi-letter ISA extensions */ -#define RISCV_ISA_EXT_BASE 26 - -/* - * These macros represent the logical ID for each multi-letter RISC-V ISA extension. - * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed - * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter - * extensions while all the multi-letter extensions should define the next - * available logical extension id. - * Entries are sorted alphabetically. + * These macros represent the logical IDs of each multi-letter RISC-V ISA + * extension and are used in the ISA bitmap. The logical IDs start from + * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single + * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order + * to allocate the bitmap and may be increased when necessary. + * + * New extensions should just be added to the bottom, rather than added + * alphabetically, in order to avoid unnecessary shuffling. */ -#define RISCV_ISA_EXT_SSCOFPMF 26 -#define RISCV_ISA_EXT_SSTC 27 -#define RISCV_ISA_EXT_SVINVAL 28 -#define RISCV_ISA_EXT_SVPBMT 29 -#define RISCV_ISA_EXT_ZBB 30 -#define RISCV_ISA_EXT_ZICBOM 31 -#define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_BASE 26 + +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SSTC 27 +#define RISCV_ISA_EXT_SVINVAL 28 +#define RISCV_ISA_EXT_SVPBMT 29 +#define RISCV_ISA_EXT_ZBB 30 +#define RISCV_ISA_EXT_ZICBOM 31 +#define RISCV_ISA_EXT_ZIHINTPAUSE 32 + +#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 #ifndef __ASSEMBLY__
While the comment above the ISA extension ID definitions says "Entries are sorted alphabetically.", this stopped being good advice with commit d8a3d8a75206 ("riscv: hwcap: make ISA extension ids can be used in asm"), as we now use macros instead of enums. Reshuffling defines is error-prone, so, since they don't need to be in any particular order, change the advice to just adding new extensions at the bottom. Also, take the opportunity to change spaces to tabs, merge three comments into one, and move the base and max defines into more logical locations wrt the ID definitions. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 42 ++++++++++++++++------------------ 1 file changed, 20 insertions(+), 22 deletions(-)