| Message ID | 20230217180035.39658-1-conor@kernel.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | dt-bindings: drop Sagar Kadam from SiFive binding maintainership | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 727 and now 727 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 2 this patch: 2 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 30 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Fri, 17 Feb 2023 10:00:36 PST (-0800), Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Sagar's email listed in maintainers is bouncing as his division was sold > off by the company. I attempted to contact him some days ago on what the > bounce email told me was his new contact information, but am yet to > receive a response. > > Paul and Palmer are listed on each of the bindings, both of whom were > alive & well as of Wednesday so the bindings remain maintained. > > CC: Sagar Kadam <sagar.kadam@openfive.com> > CC: Sagar Kadam <sagar.kadam@sifive.com> > Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Palmer/Paul, as mentioned Wednesday, here you go! Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Thanks! > --- > Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml | 1 - > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 - > Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 1 - > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 3 +-- > 4 files changed, 1 insertion(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml > index c3be1b600007..c79e752283aa 100644 > --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml > +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml > @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) > > maintainers: > - - Sagar Kadam <sagar.kadam@sifive.com> > - Paul Walmsley <paul.walmsley@sifive.com> > > description: > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 99e01f4d0a69..63bc89e13480 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -45,7 +45,6 @@ description: > from S-mode. So add thead,c900-plic to distinguish them. > > maintainers: > - - Sagar Kadam <sagar.kadam@sifive.com> > - Paul Walmsley <paul.walmsley@sifive.com> > - Palmer Dabbelt <palmer@dabbelt.com> > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > index 605c1766dba8..bae993128981 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: SiFive PWM controller > > maintainers: > - - Sagar Kadam <sagar.kadam@sifive.com> > - Paul Walmsley <paul.walmsley@sifive.com> > > description: > diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > index bf3f07421f7e..0551a0d1b3df 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > @@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: SiFive Composable Cache Controller > > maintainers: > - - Sagar Kadam <sagar.kadam@sifive.com> > - - Paul Walmsley <paul.walmsley@sifive.com> > + - Paul Walmsley <paul.walmsley@sifive.com> > > description: > The SiFive Composable Cache Controller is used to provide access to fast copies
On Fri, 17 Feb 2023 18:00:36 +0000, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Sagar's email listed in maintainers is bouncing as his division was sold > off by the company. I attempted to contact him some days ago on what the > bounce email told me was his new contact information, but am yet to > receive a response. > > Paul and Palmer are listed on each of the bindings, both of whom were > alive & well as of Wednesday so the bindings remain maintained. > > CC: Sagar Kadam <sagar.kadam@openfive.com> > CC: Sagar Kadam <sagar.kadam@sifive.com> > Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Palmer/Paul, as mentioned Wednesday, here you go! > --- > Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml | 1 - > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 - > Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 1 - > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 3 +-- > 4 files changed, 1 insertion(+), 5 deletions(-) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml index c3be1b600007..c79e752283aa 100644 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 99e01f4d0a69..63bc89e13480 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -45,7 +45,6 @@ description: from S-mode. So add thead,c900-plic to distinguish them. maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@dabbelt.com> diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml index 605c1766dba8..bae993128981 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive PWM controller maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index bf3f07421f7e..0551a0d1b3df 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Composable Cache Controller maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - - Paul Walmsley <paul.walmsley@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> description: The SiFive Composable Cache Controller is used to provide access to fast copies