| Message ID | 20230224170118.16766-10-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
Hey Andy, On Fri, Feb 24, 2023 at 05:01:08PM +0000, Andy Chiu wrote: > From: Greentime Hu <greentime.hu@sifive.com> > > This patch adds task switch support for vector. It also supports all > lengths of vlen. > > [guoren@linux.alibaba.com: First available porting to support vector > context switching] > [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and > code refine] > [vincent.chen@sifive.com: Fix the might_sleep issue in riscv_v_vstate_save, > riscv_v_vstate_restore] > [andrew@sifive.com: Optimize task switch codes of vector] > [ruinland.tsai@sifive.com: Fix the arch_release_task_struct free wrong > datap issue] > [vineetg: Fixed lkp warning with W=1 build] > [andy.chiu: Use inline asm for task switches] Can we *please* get rid of these silly changelogs in the commit messages? Either someone did something worthy of being a co-developer on the patch, or this belongs under the --- line. It's a bit ridiculous I think to have a 15 word commit message for the patch, but have like 8 different bits of per-version changelogs... > Suggested-by: Andrew Waterman <andrew@sifive.com> > Co-developed-by: Nick Knight <nick.knight@sifive.com> > Signed-off-by: Nick Knight <nick.knight@sifive.com> > Co-developed-by: Guo Ren <guoren@linux.alibaba.com> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Co-developed-by: Vincent Chen <vincent.chen@sifive.com> > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > Co-developed-by: Ruinland Tsai <ruinland.tsai@sifive.com> > Signed-off-by: Ruinland Tsai <ruinland.tsai@sifive.com> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > arch/riscv/include/asm/processor.h | 1 + > arch/riscv/include/asm/switch_to.h | 3 ++ > arch/riscv/include/asm/thread_info.h | 3 ++ > arch/riscv/include/asm/vector.h | 43 ++++++++++++++++++++++++++-- > arch/riscv/kernel/process.c | 18 ++++++++++++ > 5 files changed, 66 insertions(+), 2 deletions(-) > @@ -118,6 +154,9 @@ static __always_inline bool has_vector(void) { return false; } > static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } > #define riscv_v_vsize (0) > #define riscv_v_setup_vsize() do {} while (0) > +#define riscv_v_vstate_save(task, regs) do {} while (0) > +#define riscv_v_vstate_restore(task, regs) do {} while (0) > +#define __switch_to_vector(__prev, __next) do {} while (0) > #define riscv_v_vstate_off(regs) do {} while (0) > #define riscv_v_vstate_on(regs) do {} while (0) While you're at it, you pay as well tab out all the do {} while (0) so that they align. That's my OCD showing though. Other than my complaint about the changelogs, this looks grand. Thanks, Conor.
Conor Dooley <conor@kernel.org> writes: > Hey Andy, > > On Fri, Feb 24, 2023 at 05:01:08PM +0000, Andy Chiu wrote: >> From: Greentime Hu <greentime.hu@sifive.com> >> >> This patch adds task switch support for vector. It also supports all >> lengths of vlen. >> >> [guoren@linux.alibaba.com: First available porting to support vector >> context switching] >> [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and >> code refine] >> [vincent.chen@sifive.com: Fix the might_sleep issue in riscv_v_vstate_save, >> riscv_v_vstate_restore] >> [andrew@sifive.com: Optimize task switch codes of vector] >> [ruinland.tsai@sifive.com: Fix the arch_release_task_struct free wrong >> datap issue] >> [vineetg: Fixed lkp warning with W=1 build] >> [andy.chiu: Use inline asm for task switches] > > Can we *please* get rid of these silly changelogs in the commit messages? > Either someone did something worthy of being a co-developer on the > patch, or this belongs under the --- line. > It's a bit ridiculous I think to have a 15 word commit message for the > patch, but have like 8 different bits of per-version changelogs... Yes, please! And not only for this patch, but for the series in general. The series needs a respin for various reasons, so now would be a good opportunity to clean up the changelog. Simply move it to the cover letter, or below --- as Conor suggests.
Andy Chiu <andy.chiu@sifive.com> writes: > diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h > index f704c8dd57e0..9e28c0199030 100644 > --- a/arch/riscv/include/asm/thread_info.h > +++ b/arch/riscv/include/asm/thread_info.h > @@ -80,6 +80,9 @@ struct thread_info { > .preempt_count = INIT_PREEMPT_COUNT, \ > } > > +void arch_release_task_struct(struct task_struct *tsk); > +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); > + > #endif /* !__ASSEMBLY__ */ > > /* > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > index 9c025f2efdc3..830f9d3c356b 100644 > --- a/arch/riscv/include/asm/vector.h > +++ b/arch/riscv/include/asm/vector.h > @@ -10,6 +10,9 @@ > > #ifdef CONFIG_RISCV_ISA_V > > +#include <linux/sched.h> > +#include <linux/sched/task_stack.h> > +#include <asm/ptrace.h> > #include <asm/hwcap.h> > #include <asm/csr.h> > #include <asm/asm.h> > @@ -75,7 +78,8 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src > "r" (src->vcsr) :); > } > > -static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, void *datap) > +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, > + void *datap) Please avoid code churn like this... > { > riscv_v_enable(); > __vstate_csr_save(save_to); > @@ -93,7 +97,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, vo > } > > static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_from, > - void *datap) > + void *datap) ...and this. > { > riscv_v_enable(); > asm volatile ( > @@ -110,6 +114,38 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ > riscv_v_disable(); > } > > +static inline void riscv_v_vstate_save(struct task_struct *task, > + struct pt_regs *regs) > +{ > + if ((regs->status & SR_VS) == SR_VS_DIRTY) { > + struct __riscv_v_ext_state *vstate = &task->thread.vstate; > + > + __riscv_v_vstate_save(vstate, vstate->datap); > + __riscv_v_vstate_clean(regs); > + } > +} > + > +static inline void riscv_v_vstate_restore(struct task_struct *task, > + struct pt_regs *regs) > +{ > + if ((regs->status & SR_VS) != SR_VS_OFF) { > + struct __riscv_v_ext_state *vstate = &task->thread.vstate; > + > + __riscv_v_vstate_restore(vstate, vstate->datap); > + __riscv_v_vstate_clean(regs); > + } > +} > + > +static inline void __switch_to_vector(struct task_struct *prev, > + struct task_struct *next) > +{ > + struct pt_regs *regs; > + > + regs = task_pt_regs(prev); > + riscv_v_vstate_save(prev, regs); > + riscv_v_vstate_restore(next, task_pt_regs(next)); > +} > + > #else /* ! CONFIG_RISCV_ISA_V */ > > struct pt_regs; > @@ -118,6 +154,9 @@ static __always_inline bool has_vector(void) { return false; } > static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } > #define riscv_v_vsize (0) > #define riscv_v_setup_vsize() do {} while (0) > +#define riscv_v_vstate_save(task, regs) do {} while (0) > +#define riscv_v_vstate_restore(task, regs) do {} while (0) > +#define __switch_to_vector(__prev, __next) do {} while (0) > #define riscv_v_vstate_off(regs) do {} while (0) > #define riscv_v_vstate_on(regs) do {} while (0) > > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c > index 8955f2432c2d..5e9506a32fbe 100644 > --- a/arch/riscv/kernel/process.c > +++ b/arch/riscv/kernel/process.c > @@ -24,6 +24,7 @@ > #include <asm/switch_to.h> > #include <asm/thread_info.h> > #include <asm/cpuidle.h> > +#include <asm/vector.h> > > register unsigned long gp_in_global __asm__("gp"); > > @@ -148,12 +149,28 @@ void flush_thread(void) > fstate_off(current, task_pt_regs(current)); > memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); > #endif > +#ifdef CONFIG_RISCV_ISA_V > + /* Reset vector state */ > + riscv_v_vstate_off(task_pt_regs(current)); > + kfree(current->thread.vstate.datap); > + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); > +#endif > +} > + > +void arch_release_task_struct(struct task_struct *tsk) > +{ > + /* Free the vector context of datap. */ > + if (has_vector() && tsk->thread.vstate.datap) ^^^^^^^^^^^^^^^^^^^^^^^^ No need to check for !NULL. Björn
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..f0ddf691ac5e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_ext_state vstate; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 4b96b13dee27..a727be723c56 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include <linux/jump_label.h> #include <linux/sched/task_stack.h> +#include <asm/vector.h> #include <asm/hwcap.h> #include <asm/processor.h> #include <asm/ptrace.h> @@ -78,6 +79,8 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ + if (has_vector()) \ + __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index f704c8dd57e0..9e28c0199030 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -80,6 +80,9 @@ struct thread_info { .preempt_count = INIT_PREEMPT_COUNT, \ } +void arch_release_task_struct(struct task_struct *tsk); +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); + #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 9c025f2efdc3..830f9d3c356b 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -10,6 +10,9 @@ #ifdef CONFIG_RISCV_ISA_V +#include <linux/sched.h> +#include <linux/sched/task_stack.h> +#include <asm/ptrace.h> #include <asm/hwcap.h> #include <asm/csr.h> #include <asm/asm.h> @@ -75,7 +78,8 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src "r" (src->vcsr) :); } -static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, void *datap) +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, + void *datap) { riscv_v_enable(); __vstate_csr_save(save_to); @@ -93,7 +97,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, vo } static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_from, - void *datap) + void *datap) { riscv_v_enable(); asm volatile ( @@ -110,6 +114,38 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_disable(); } +static inline void riscv_v_vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_DIRTY) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_save(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void riscv_v_vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) != SR_VS_OFF) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_restore(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + riscv_v_vstate_save(prev, regs); + riscv_v_vstate_restore(next, task_pt_regs(next)); +} + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; @@ -118,6 +154,9 @@ static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_setup_vsize() do {} while (0) +#define riscv_v_vstate_save(task, regs) do {} while (0) +#define riscv_v_vstate_restore(task, regs) do {} while (0) +#define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 8955f2432c2d..5e9506a32fbe 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -24,6 +24,7 @@ #include <asm/switch_to.h> #include <asm/thread_info.h> #include <asm/cpuidle.h> +#include <asm/vector.h> register unsigned long gp_in_global __asm__("gp"); @@ -148,12 +149,28 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_RISCV_ISA_V + /* Reset vector state */ + riscv_v_vstate_off(task_pt_regs(current)); + kfree(current->thread.vstate.datap); + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); +#endif +} + +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector() && tsk->thread.vstate.datap) + kfree(tsk->thread.vstate.datap); } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); *dst = *src; + /* clear entire V context, including datap for a new task */ + memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); + return 0; } @@ -186,6 +203,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) childregs->a0 = 0; /* Return value of fork() */ p->thread.ra = (unsigned long)ret_from_fork; } + riscv_v_vstate_off(childregs); p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; }