From patchwork Sat Mar 11 09:07:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 13170695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1EC4C74A5B for ; Sat, 11 Mar 2023 09:08:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=APn/VTbxTmts8WfO1v6R5ryHLTC02mt/nosgeef2Zjs=; b=V+6AXMXLswtHPX jy/ctEoJjM8tIcQ2VyttEIsEqvdGsc/Cp9LEd5/x173Iqeg8pcNU1ZHr/cFAJE2Ny5Ajs1NHL5cn7 WtpV+nGiKlgH/cHyBhWznoMM282ruUUzvTNg6WVCerUXCbYjJfHRdCVz36cfYQXkQXvJ9G5Wc+6z7 jwmzhlndQCU4KG0pprAb0kw6zb49cDHKlwpyORbRkRammFafq8Okiwxcxi3SmMGxqvvaNEdJusnQv VFhunAacoQ4QGrnw9MV04jhLh6WAazCuXjT4zFBJpHTOuMfpSJz6D+wzTnkJikFr3cKBgQ5R4H2rF 3aakiQQHq4tvE7Yc0uTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pavDY-00HZAt-Ky; Sat, 11 Mar 2023 09:08:44 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pavDI-00HYwm-IX for linux-riscv@lists.infradead.org; Sat, 11 Mar 2023 09:08:33 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4247B24E1BA; Sat, 11 Mar 2023 17:07:45 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sat, 11 Mar 2023 17:07:45 +0800 Received: from ubuntu.localdomain (183.27.96.115) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sat, 11 Mar 2023 17:07:44 +0800 From: Hal Feng To: , , CC: Stephen Boyd , Michael Turquette , Philipp Zabel , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Paul Walmsley , Albert Ou , Ben Dooks , "Daniel Lezcano" , Thomas Gleixner , Marc Zyngier , Emil Renner Berthing , Hal Feng , Subject: [PATCH v5 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Date: Sat, 11 Mar 2023 17:07:22 +0800 Message-ID: <20230311090733.56918-11-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230311090733.56918-1-hal.feng@starfivetech.com> References: <20230311090733.56918-1-hal.feng@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.115] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230311_010829_008607_4DA666A4 X-CRM114-Status: GOOD ( 17.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Emil Renner Berthing We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai Reviewed-by: Conor Dooley Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng --- .../reset/starfive/reset-starfive-jh7100.c | 14 ++++----- .../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++---------- .../reset/starfive/reset-starfive-jh71x0.h | 2 +- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c index 5f06e5ae3346..2a56f7fd4ba7 100644 --- a/drivers/reset/starfive/reset-starfive-jh7100.c +++ b/drivers/reset/starfive/reset-starfive-jh7100.c @@ -30,16 +30,16 @@ * lines don't though, so store the expected value of the status registers when * all lines are asserted. */ -static const u64 jh7100_reset_asserted[2] = { +static const u32 jh7100_reset_asserted[4] = { /* STATUS0 */ - BIT_ULL_MASK(JH7100_RST_U74) | - BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | - BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | + BIT(JH7100_RST_U74 % 32) | + BIT(JH7100_RST_VP6_DRESET % 32) | + BIT(JH7100_RST_VP6_BRESET % 32), /* STATUS1 */ - BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | - BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), + BIT(JH7100_RST_HIFI4_DRESET % 32) | + BIT(JH7100_RST_HIFI4_BRESET % 32), /* STATUS2 */ - BIT_ULL_MASK(JH7100_RST_E24) | + BIT(JH7100_RST_E24 % 32), /* STATUS3 */ 0, }; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c index a689f4730ed7..55bbbd2de52c 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -21,7 +20,7 @@ struct jh71x0_reset { spinlock_t lock; void __iomem *assert; void __iomem *status; - const u64 *asserted; + const u32 *asserted; }; static inline struct jh71x0_reset * @@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_assert = data->assert + offset * sizeof(u64); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 done = data->asserted ? data->asserted[offset] & mask : 0; - u64 value; + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_assert = data->assert + offset * sizeof(u32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 done = data->asserted ? data->asserted[offset] & mask : 0; + u32 value; unsigned long flags; int ret; @@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, spin_lock_irqsave(&data->lock, flags); - value = readq(reg_assert); + value = readl(reg_assert); if (assert) value |= mask; else value &= ~mask; - writeq(value, reg_assert); + writel(value, reg_assert); /* if the associated clock is gated, deasserting might otherwise hang forever */ - ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); + ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); spin_unlock_irqrestore(&data->lock, flags); return ret; @@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct jh71x0_reset *data = jh71x0_reset_from(rcdev); - unsigned long offset = BIT_ULL_WORD(id); - u64 mask = BIT_ULL_MASK(id); - void __iomem *reg_status = data->status + offset * sizeof(u64); - u64 value = readq(reg_status); + unsigned long offset = id / 32; + u32 mask = BIT(id % 32); + void __iomem *reg_status = data->status + offset * sizeof(u32); + u32 value = readl(reg_status); return !((value ^ data->asserted[offset]) & mask); } @@ -107,7 +106,7 @@ static const struct reset_control_ops jh71x0_reset_ops = { int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner) { struct jh71x0_reset *data; diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h index ac9e80dd3f59..db7d39a87f87 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -8,7 +8,7 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, void __iomem *assert, void __iomem *status, - const u64 *asserted, unsigned int nr_resets, + const u32 *asserted, unsigned int nr_resets, struct module *owner); #endif /* __RESET_STARFIVE_JH71X0_H */