| Message ID | 20230316030514.137427-2-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PLL clocks driver for StarFive JH7110 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On 16/03/2023 04:05, Xingyu Wu wrote: > Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > + > +examples: > + - | > + pllclk: pll-clock-controller { This should be just "clock-controller" (and drop the label). With above Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 2023/3/19 20:25, Krzysztof Kozlowski wrote: > On 16/03/2023 04:05, Xingyu Wu wrote: >> Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > > >> + >> +examples: >> + - | >> + pllclk: pll-clock-controller { > > This should be just "clock-controller" (and drop the label). Will modify to "clock-controller" and drop the label. Thanks. > > With above > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Best regards, Xingyu Wu
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..9397516f60ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + This PLL are high speed, low jitter frequency synthesizers in JH7110. + Each PLL clocks work in integer mode or fraction mode by some dividers, + and the configuration registers and dividers are set in several syscon + registers. So pll node should be a child of SYS-SYSCON node. + The formula for calculating frequency is that, + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + pllclk: pll-clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..086a6ddcf380 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -6,6 +6,12 @@ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_CLK_PLL0_OUT 0 +#define JH7110_CLK_PLL1_OUT 1 +#define JH7110_CLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml