From patchwork Fri Mar 17 11:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13178977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97E6DC7618B for ; Fri, 17 Mar 2023 11:37:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Z6sUKyI3m5XMLlB+VlT2/quobJXYLJLmRBqkxVAiJiY=; b=UqnPCnPrODzlWcl7E1La1w28T4 VVYYP3yZR/kTnK1DhF/k3PeFon7pNJF0eRZ/ByIZyFnJU62OF0vZaaCda4NvXHxTWztN4JVlULy81 gTr7PF5/xLHZcDoADaOhq9TWyzYe/VeNAqIuAEc1evH/4KDnUXvIEotdhSAcs5p24TGAZwpo99Ae7 YINVW/39YR6tdZNeKSwlTHZcL5K5KoTZm2GAEIMIezNMooBM0nf8Ekcnes4HW0Qm/pKBDUmuzDSbf Az7psYHGJCv6s+seaTpwtKBGGT44Xvn3YiUwI3MJBZDY4VkbIwosub4DHWmQXfUUpF2PyFxoB+u3A Imw0b9LA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pd8Oc-0025Iy-1T; Fri, 17 Mar 2023 11:37:18 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pd8OZ-0025Gx-0k for linux-riscv@lists.infradead.org; Fri, 17 Mar 2023 11:37:16 +0000 Received: by mail-pl1-x634.google.com with SMTP id ja10so4993643plb.5 for ; Fri, 17 Mar 2023 04:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1679053034; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=NcKTsCTSmNOhC0Xny21sgBkTMqUxDz8AQSzRNkwiV+c=; b=LAnYMr8AniVKHebGhBlbV/2nzpRatI7lW9XonCtjrl2kftaZP/1/PiCjWoGUqdEDFW MgsnXwJsDEWp+YFA6tceWNzcL/qJ/75pYcJWglJIUL1gRZDqZbDDzkb+LSu4TrHDgMdX u/nKZIXYRdisfr7tgm3OTyljtPU4m8v+j4M6h96ikhEC7EEXB2yfnVRawT/RJVvhqRUz iYkHLvy76ACzb97ywLtW6gM/acbJRBxvD0uWvdo2tGrp5fT85UjNIES1PomkMrVMdp74 yjVya0iKKnSz4vo7xTQrlqS1lyLtzokHdm5dm9NqoFQ04k4YPgxKNPecurklk+Ivfmqc lOsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679053034; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NcKTsCTSmNOhC0Xny21sgBkTMqUxDz8AQSzRNkwiV+c=; b=xHbLG7mFUXnsEbj+38CKO9GvxXUw137JT8F0Dx1VrdvywAFWfy98DqJB1fXiEubHIx QkXkHuMTRBFNTP8anVano+Ty6a32a4ngE32bS61UpXJmcSKfv7+lX78hVS6FkNZpTjIl GHCQrOl3J5iuwXhgmCmnx2Y+Bt+61WxnCz0B/Dgv4RM7ya0cIeu6nVo1o8UD0sJ1Yzkw ubzeDYhG9A5kEhl3Kb4/vY/Flxq4bQgnJnY+EyP5dV8F3hPNaobiLTXj/CIaUQi93g26 8IhxDyDEHQ124SSIH9031QhCfsDbXiNch6fABBFYWlB9IXpXdIydaMciNVUMLS59rQnQ XtiA== X-Gm-Message-State: AO0yUKUHABEwDw26Z/zV+xYx7OVxcATjO+0xJ0bF9XbdYcra0pqo/lDL 7h4+zS3eWJd0pjOEbuNubCVljVZ5hAeEz7TK1bZNMmqWuh/7BnqoGR+YD7QKAQJj5rQZqa/R9kY aUFonH2hUHHT11uxiunwSiDbIh/YXqif6MugKhsU/QEGgNIQa2K9kSU6jRxYkogey6dt2EL0lji Q9ZWE3zpk6Sddr X-Google-Smtp-Source: AK7set/mxVr12xBwqvn4nHRgAfEiBiEHjZfBQMOzh8WHQXZt2LI3VSTLxV6Al1KQ3YU7Q7p2y7x7cg== X-Received: by 2002:a17:90b:1e11:b0:23d:1e5f:eea6 with SMTP id pg17-20020a17090b1e1100b0023d1e5feea6mr8134234pjb.24.1679053034131; Fri, 17 Mar 2023 04:37:14 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id n63-20020a17090a2cc500b0023d3845b02bsm1188740pjd.45.2023.03.17.04.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 04:37:13 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Subject: [PATCH -next v15 09/19] riscv: Add task switch support for vector Date: Fri, 17 Mar 2023 11:35:28 +0000 Message-Id: <20230317113538.10878-10-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com> References: <20230317113538.10878-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230317_043715_270223_7F73C538 X-CRM114-Status: GOOD ( 17.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kefeng Wang , guoren@linux.alibaba.com, Jisheng Zhang , Nick Knight , Peter Zijlstra , vineetg@rivosinc.com, "Eric W. Biederman" , Vincent Chen , Conor Dooley , Albert Ou , Guo Ren , Ruinland Tsai , Andy Chiu , Paul Walmsley , greentime.hu@sifive.com, Dmitry Vyukov , Heiko Stuebner MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Greentime Hu This patch adds task switch support for vector. It also supports all lengths of vlen. Suggested-by: Andrew Waterman Co-developed-by: Nick Knight Signed-off-by: Nick Knight Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Ruinland Tsai Signed-off-by: Ruinland Tsai Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Björn Töpel --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/include/asm/thread_info.h | 3 +++ arch/riscv/include/asm/vector.h | 38 ++++++++++++++++++++++++++++ arch/riscv/kernel/process.c | 18 +++++++++++++ 5 files changed, 63 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..f0ddf691ac5e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_ext_state vstate; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 4b96b13dee27..a727be723c56 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -78,6 +79,8 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ + if (has_vector()) \ + __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index f704c8dd57e0..9e28c0199030 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -80,6 +80,9 @@ struct thread_info { .preempt_count = INIT_PREEMPT_COUNT, \ } +void arch_release_task_struct(struct task_struct *tsk); +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); + #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index c7143b7d64d1..3bfa223facd0 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,6 +11,9 @@ #ifdef CONFIG_RISCV_ISA_V #include +#include +#include +#include #include #include #include @@ -123,6 +126,38 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_disable(); } +static inline void riscv_v_vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_DIRTY) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_save(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void riscv_v_vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) != SR_VS_OFF) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_restore(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + riscv_v_vstate_save(prev, regs); + riscv_v_vstate_restore(next, task_pt_regs(next)); +} + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; @@ -131,6 +166,9 @@ static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_setup_vsize() do {} while (0) +#define riscv_v_vstate_save(task, regs) do {} while (0) +#define riscv_v_vstate_restore(task, regs) do {} while (0) +#define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 774ffde386ab..44ca0be58ce7 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -24,6 +24,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -147,12 +148,28 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_RISCV_ISA_V + /* Reset vector state */ + riscv_v_vstate_off(task_pt_regs(current)); + kfree(current->thread.vstate.datap); + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); +#endif +} + +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector()) + kfree(tsk->thread.vstate.datap); } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); *dst = *src; + /* clear entire V context, including datap for a new task */ + memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); + return 0; } @@ -185,6 +202,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) childregs->a0 = 0; /* Return value of fork() */ p->thread.ra = (unsigned long)ret_from_fork; } + riscv_v_vstate_off(childregs); p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; }