[-next,v16,17/20] riscv: kvm: Add V extension to KVM ISA

Message ID	20230323145924.4194-18-andy.chiu@sifive.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH -next v16 17/20] riscv: kvm: Add V extension to KVM ISA Date: Thu, 23 Mar 2023 14:59:21 +0000 Message-Id: <20230323145924.4194-18-andy.chiu@sifive.com> In-Reply-To: <20230323145924.4194-1-andy.chiu@sifive.com> References: <20230323145924.4194-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v16,00/20] riscv: Add vector ISA support [-next,v16,01/20] riscv: Rename __switch_to_aux() -> fpu [-next,v16,02/20] riscv: Extending cpufeature.c to detect V-extension [-next,v16,03/20] riscv: Add new csr defines related to vector extension [-next,v16,04/20] riscv: Clear vector regfile on bootup [-next,v16,05/20] riscv: Disable Vector Instructions for kernel itself [-next,v16,06/20] riscv: Introduce Vector enable/disable helpers [-next,v16,07/20] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v16,08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v16,09/20] riscv: Add task switch support for vector [-next,v16,10/20] riscv: Allocate user's vector context in the first-use trap [-next,v16,11/20] riscv: Add ptrace vector support [-next,v16,12/20] riscv: signal: check fp-reserved words unconditionally [-next,v16,13/20] riscv: signal: Add sigcontext save/restore for vector [-next,v16,14/20] riscv: signal: Report signal frame size to userspace via auxv [-next,v16,15/20] riscv: signal: validate altstack to reflect Vector [-next,v16,16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v16,17/20] riscv: kvm: Add V extension to KVM ISA [-next,v16,18/20] riscv: KVM: Add vector lazy save/restore support [-next,v16,19/20] riscv: detect assembler support for .option arch [-next,v16,20/20] riscv: Enable Vector code to be built

Message ID

20230323145924.4194-18-andy.chiu@sifive.com (mailing list archive)

State

Superseded

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Vincent Chen <vincent.chen@sifive.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH -next v16 17/20] riscv: kvm: Add V extension to KVM ISA
Date: Thu, 23 Mar 2023 14:59:21 +0000
Message-Id: <20230323145924.4194-18-andy.chiu@sifive.com>
In-Reply-To: <20230323145924.4194-1-andy.chiu@sifive.com>
References: <20230323145924.4194-1-andy.chiu@sifive.com>
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

riscv: Add vector ISA support | expand

Context	Check	Description
conchuod/apply	fail	Patch does not apply to for-next
conchuod/tree_selection	fail	Failed to apply to next/pending-fixes or riscv/for-next

Context

Check

Description

conchuod/apply

fail

Patch does not apply to for-next

conchuod/tree_selection

fail

Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Andy Chiu March 23, 2023, 2:59 p.m. UTC

From: Vincent Chen <vincent.chen@sifive.com>

Add V extension to KVM isa extension list to enable supporting of V
extension on VCPUs.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index e44c1e90eaa7..d562dcb929ea 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -107,6 +107,7 @@  enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
 	KVM_RISCV_ISA_EXT_ZICBOM,
 	KVM_RISCV_ISA_EXT_ZICBOZ,
+	KVM_RISCV_ISA_EXT_V,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 6adb1b6112a1..bfdd5b73d462 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -57,6 +57,7 @@  static const unsigned long kvm_isa_ext_arr[] = {
 	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
 	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
 	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
+	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
 
 	KVM_ISA_EXT_ARR(SSTC),
 	KVM_ISA_EXT_ARR(SVINVAL),

[-next,v16,17/20] riscv: kvm: Add V extension to KVM ISA

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Patch