[-next,v16,20/20] riscv: Enable Vector code to be built

Message ID	20230323145924.4194-21-andy.chiu@sifive.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH -next v16 20/20] riscv: Enable Vector code to be built Date: Thu, 23 Mar 2023 14:59:24 +0000 Message-Id: <20230323145924.4194-21-andy.chiu@sifive.com> In-Reply-To: <20230323145924.4194-1-andy.chiu@sifive.com> References: <20230323145924.4194-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v16,00/20] riscv: Add vector ISA support [-next,v16,01/20] riscv: Rename __switch_to_aux() -> fpu [-next,v16,02/20] riscv: Extending cpufeature.c to detect V-extension [-next,v16,03/20] riscv: Add new csr defines related to vector extension [-next,v16,04/20] riscv: Clear vector regfile on bootup [-next,v16,05/20] riscv: Disable Vector Instructions for kernel itself [-next,v16,06/20] riscv: Introduce Vector enable/disable helpers [-next,v16,07/20] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v16,08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v16,09/20] riscv: Add task switch support for vector [-next,v16,10/20] riscv: Allocate user's vector context in the first-use trap [-next,v16,11/20] riscv: Add ptrace vector support [-next,v16,12/20] riscv: signal: check fp-reserved words unconditionally [-next,v16,13/20] riscv: signal: Add sigcontext save/restore for vector [-next,v16,14/20] riscv: signal: Report signal frame size to userspace via auxv [-next,v16,15/20] riscv: signal: validate altstack to reflect Vector [-next,v16,16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v16,17/20] riscv: kvm: Add V extension to KVM ISA [-next,v16,18/20] riscv: KVM: Add vector lazy save/restore support [-next,v16,19/20] riscv: detect assembler support for .option arch [-next,v16,20/20] riscv: Enable Vector code to be built

Message ID

20230323145924.4194-21-andy.chiu@sifive.com (mailing list archive)

State

Superseded

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH -next v16 20/20] riscv: Enable Vector code to be built
Date: Thu, 23 Mar 2023 14:59:24 +0000
Message-Id: <20230323145924.4194-21-andy.chiu@sifive.com>
In-Reply-To: <20230323145924.4194-1-andy.chiu@sifive.com>
References: <20230323145924.4194-1-andy.chiu@sifive.com>
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Series

riscv: Add vector ISA support | expand

Context	Check	Description
conchuod/apply	fail	Patch does not apply to for-next
conchuod/tree_selection	fail	Failed to apply to next/pending-fixes or riscv/for-next

Context

Check

Description

conchuod/apply

fail

Patch does not apply to for-next

conchuod/tree_selection

fail

Failed to apply to next/pending-fixes or riscv/for-next

Commit Message

Andy Chiu March 23, 2023, 2:59 p.m. UTC

From: Guo Ren <guoren@linux.alibaba.com>

This patch adds a config which enables vector feature from the kernel
space.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Suggested-by: Vineet Gupta <vineetg@rivosinc.com>
Suggested-by: Atish Patra <atishp@atishpatra.org>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig  | 20 ++++++++++++++++++++
 arch/riscv/Makefile |  6 +++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4f8fd4002f1d..0e0377b5319c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -442,6 +442,26 @@  config RISCV_ISA_SVPBMT
 
 	   If you don't know what to do here, say Y.
 
+config TOOLCHAIN_HAS_V
+	bool
+	default y
+	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
+	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
+	depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
+	depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_V
+	bool "VECTOR extension support"
+	depends on TOOLCHAIN_HAS_V
+	depends on FPU
+	select DYNAMIC_SIGFRAME
+	default y
+	help
+	  Say N here if you want to disable all vector related procedure
+	  in the kernel.
+
+	  If you don't know what to do here, say Y.
+
 config TOOLCHAIN_HAS_ZBB
 	bool
 	default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6203c3378922..6f32c0ab32e3 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -56,6 +56,7 @@  riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
 riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
 riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+riscv-march-$(CONFIG_RISCV_ISA_V)	:= $(riscv-march-y)v
 
 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.
@@ -65,7 +66,10 @@  riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
 # Check if the toolchain supports Zihintpause extension
 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
 
-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
+# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
+KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
+
 KBUILD_AFLAGS += -march=$(riscv-march-y)
 
 KBUILD_CFLAGS += -mno-save-restore

[-next,v16,20/20] riscv: Enable Vector code to be built

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