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Wed, 19 Apr 2023 04:10:15 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:14 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?utf-8?q?Kornel_Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 04/21] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Date: Wed, 19 Apr 2023 04:10:54 -0700 Message-Id: <20230419111111.477118-5-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230419_041018_576530_CEA8E4CA X-CRM114-Status: GOOD ( 13.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define data structures to store the capacity and bandwidth capabilities that are discovered for a CBQRI-capable controller. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 130 +++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 arch/riscv/kernel/qos/internal.h diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/internal.h new file mode 100644 index 000000000000..e07d7f92e206 --- /dev/null +++ b/arch/riscv/kernel/qos/internal.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_QOS_INTERNAL_H +#define _ASM_RISCV_QOS_INTERNAL_H + +#include + +#define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_MON_CTL_OFF 8 +#define CBQRI_CC_MON_CTL_VAL_OFF 16 +#define CBQRI_CC_ALLOC_CTL_OFF 24 +#define CBQRI_CC_BLOCK_MASK_OFF 32 + +#define CBQRI_BC_CAPABILITIES_OFF 0 +#define CBQRI_BC_MON_CTL_OFF 8 +#define CBQRI_BC_MON_CTR_VAL_OFF 16 +#define CBQRI_BC_ALLOC_CTL_OFF 24 +#define CBQRI_BC_BW_ALLOC_OFF 32 + +#define CBQRI_CC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_CC_CAPABILITIES_FRCID_MASK 0x1 +#define CBQRI_CC_CAPABILITIES_FRCID_SHIFT 24 + +#define CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT 8 +#define CBQRI_CC_CAPABILITIES_NCBLKS_MASK 0xFFFF + +#define CBQRI_BC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT 8 +#define CBQRI_BC_CAPABILITIES_NBWBLKS_MASK 0xFFFF +#define CBQRI_BC_CAPABILITIES_MRBWB_SHIFT 32 +#define CBQRI_BC_CAPABILITIES_MRBWB_MASK 0xFFFF + +#define CBQRI_CONTROL_REGISTERS_BUSY_SHIFT 39 +#define CBQRI_CONTROL_REGISTERS_BUSY_MASK 0x01 +#define CBQRI_CONTROL_REGISTERS_STATUS_SHIFT 32 +#define CBQRI_CONTROL_REGISTERS_STATUS_MASK 0x7F +#define CBQRI_CONTROL_REGISTERS_OP_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_OP_MASK 0x1F +#define CBQRI_CONTROL_REGISTERS_AT_SHIFT 5 +#define CBQRI_CONTROL_REGISTERS_AT_MASK 0x07 +#define CBQRI_CONTROL_REGISTERS_AT_DATA 0 +#define CBQRI_CONTROL_REGISTERS_AT_CODE 1 +#define CBQRI_CONTROL_REGISTERS_RCID_SHIFT 8 +#define CBQRI_CONTROL_REGISTERS_RCID_MASK 0xFFF +#define CBQRI_CONTROL_REGISTERS_RBWB_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_RBWB_MASK 0xFF + +#define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_CC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_CC_ALLOC_CTL_OP_FLUSH_RCID 3 +#define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_BC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 + +/* Capacity Controller hardware capabilities */ +/* from qemu/include/hw/riscv/cbqri.h */ +struct riscv_cbqri_capacity_caps { + u16 ncblks; + u16 cache_level; + u32 blk_size; + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + bool supports_alloc_op_flush_rcid; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_occupancy; +}; + +/* Bandwidth Controller hardware capabilities */ +/* from qemu/include/hw/riscv/cbqri.h */ +struct riscv_cbqri_bandwidth_caps { + u16 nbwblks; /* number of bandwidth block */ + u16 mrbwb; /* max reserved bw blocks */ + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +}; + +struct cbqri_controller { + struct cbqri_controller_info *ctrl_info; + void __iomem *base; + + int ver_major; + int ver_minor; + + struct riscv_cbqri_bandwidth_caps bc; + struct riscv_cbqri_capacity_caps cc; + + bool alloc_capable; + bool mon_capable; +}; + +#endif /* _ASM_RISCV_QOS_INTERNAL_H */