| Message ID | 20230518161949.11203-4-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 249 this patch: 249 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 918 this patch: 918 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Prefer using the BIT macro |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, May 18, 2023 at 9:20 AM Andy Chiu <andy.chiu@sifive.com> wrote: > > Probing kernel support for Vector extension is available now. This only > add detection for V only. Extenions like Zvfh, Zk are not in this scope. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Thanks Andy! Reviewed-by: Evan Green <evan@rivosinc.com> ps- This will end up conflicting with my patch which moves that hunk to a helper function, and also allocates the same hwprobe bit [1]. The fixup is very straightforward for a human, so the ordering isn't a big deal either way. But I thought I'd give you a heads up so you weren't surprised if someone mentioned it. [1] https://lore.kernel.org/lkml/20230509182504.2997252-4-evan@rivosinc.com/
On Thu, 18 May 2023 09:19:26 PDT (-0700), andy.chiu@sifive.com wrote: > Probing kernel support for Vector extension is available now. This only > add detection for V only. Extenions like Zvfh, Zk are not in this scope. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Changelog v20: > - Fix a typo in document, and remove duplicated probes (Heiko) > - probe V extension in RISCV_HWPROBE_KEY_IMA_EXT_0 key only (Palmer, > Evan) > --- > Documentation/riscv/hwprobe.rst | 3 +++ > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/sys_riscv.c | 4 ++++ > 3 files changed, 8 insertions(+) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..7431d9d01c73 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -64,6 +64,9 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > + * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by > + version 1.0 of the RISC-V Vector extension manual. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..7c6fdcf7ced5 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -25,6 +25,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > +#define RISCV_HWPROBE_IMA_V (1 << 2) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..88357a848797 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -10,6 +10,7 @@ > #include <asm/cpufeature.h> > #include <asm/hwprobe.h> > #include <asm/sbi.h> > +#include <asm/vector.h> > #include <asm/switch_to.h> > #include <asm/uaccess.h> > #include <asm/unistd.h> > @@ -171,6 +172,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > if (riscv_isa_extension_available(NULL, c)) > pair->value |= RISCV_HWPROBE_IMA_C; > > + if (has_vector()) > + pair->value |= RISCV_HWPROBE_IMA_V; > + > break; > > case RISCV_HWPROBE_KEY_CPUPERF_0: Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
On Fri, May 19, 2023 at 12:20 AM Andy Chiu <andy.chiu@sifive.com> wrote: > > Probing kernel support for Vector extension is available now. This only > add detection for V only. Extenions like Zvfh, Zk are not in this scope. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Guo Ren <guoren@kernel.org> > --- > Changelog v20: > - Fix a typo in document, and remove duplicated probes (Heiko) > - probe V extension in RISCV_HWPROBE_KEY_IMA_EXT_0 key only (Palmer, > Evan) > --- > Documentation/riscv/hwprobe.rst | 3 +++ > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/sys_riscv.c | 4 ++++ > 3 files changed, 8 insertions(+) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..7431d9d01c73 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -64,6 +64,9 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > + * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by > + version 1.0 of the RISC-V Vector extension manual. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..7c6fdcf7ced5 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -25,6 +25,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > +#define RISCV_HWPROBE_IMA_V (1 << 2) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..88357a848797 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -10,6 +10,7 @@ > #include <asm/cpufeature.h> > #include <asm/hwprobe.h> > #include <asm/sbi.h> > +#include <asm/vector.h> > #include <asm/switch_to.h> > #include <asm/uaccess.h> > #include <asm/unistd.h> > @@ -171,6 +172,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > if (riscv_isa_extension_available(NULL, c)) > pair->value |= RISCV_HWPROBE_IMA_C; > > + if (has_vector()) > + pair->value |= RISCV_HWPROBE_IMA_V; > + > break; > > case RISCV_HWPROBE_KEY_CPUPERF_0: > -- > 2.17.1 >
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..7431d9d01c73 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by + version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..7c6fdcf7ced5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_IMA_V (1 << 2) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..88357a848797 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -10,6 +10,7 @@ #include <asm/cpufeature.h> #include <asm/hwprobe.h> #include <asm/sbi.h> +#include <asm/vector.h> #include <asm/switch_to.h> #include <asm/uaccess.h> #include <asm/unistd.h> @@ -171,6 +172,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |= RISCV_HWPROBE_IMA_C; + if (has_vector()) + pair->value |= RISCV_HWPROBE_IMA_V; + break; case RISCV_HWPROBE_KEY_CPUPERF_0:
Probing kernel support for Vector extension is available now. This only add detection for V only. Extenions like Zvfh, Zk are not in this scope. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- Changelog v20: - Fix a typo in document, and remove duplicated probes (Heiko) - probe V extension in RISCV_HWPROBE_KEY_IMA_EXT_0 key only (Palmer, Evan) --- Documentation/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 4 ++++ 3 files changed, 8 insertions(+)