From patchwork Mon Jun 5 11:07:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E15CEC7EE23 for ; Mon, 5 Jun 2023 15:42:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TWSci5rtOKgUN9siDKhZUTGVSFdsyON/J8VryeaquwQ=; b=NOAE3v5CsFm0Tn o/FR4oLm9oMeDyf80GA0tcdgHZC0WCV2Gbi6HJ/deK6vuMpePaInPMpYl/SaJSRHFLZg87BNSEly4 wv7lzdBqmTr0ej0ZLG0amaxZA8UcFvhM7/67Wfy57CHExkYfMFsmmANjbNWZDlqMPsBYKgbqoRvks ZPw7KfWsvmW3lj0aXZlX1IpMnu+45Ws0/JcmxANBjn2TTMVOaObhGGQNUOop/V+PRz/5tGs2PG1so uyNqwWsvQJTCrK6cyAzf8laoayG7j7Zkx9hpwV7QWpHnqCReVp/JdX9EtWbYh9ocNs4Q6ZprfBtyD rnATqdtZ54xZBC4odi5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6CLa-00G0S9-2w; Mon, 05 Jun 2023 15:42:18 +0000 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6CLX-00G0P1-0H for linux-riscv@lists.infradead.org; Mon, 05 Jun 2023 15:42:16 +0000 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1b024e29657so22419365ad.3 for ; Mon, 05 Jun 2023 08:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979734; x=1688571734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LQpOfl8clKnd1O4gu74PSUiT4R3rCnMiThuoNKoAYLc=; b=dGIoYaTIu/Go0aZBEJDRNP5bu0ysEvnifzxjUTmQ7mGdMzkbzkinDQqDiPgMIKsSeq Ym8QRUeTI5rCwPZwfSEOHk/wxdk8DFHr1eHQnbcksySVaY6hz03rTPeuaDXtZpvK++pX oFu5BlBhLvkuBcR16vlbpSoHbf0Fthcw1u8Q9rRKwp8vPdW14gNni4kpC2No1tkBQUv4 vvMydl8riJBK26l7+we9Nyunz+D6OxLs38UInhGoJCYtIlnBaS5gVcX8YfyCsJOkgsSy O44vtV1RrSqGaBvNoR+pZnTMYLobVs2CRbUU9WxtEVmSuD4ChyeQQA/f+K4OyIsR5c7R Kvxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979734; x=1688571734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LQpOfl8clKnd1O4gu74PSUiT4R3rCnMiThuoNKoAYLc=; b=FVDRZ6Xt/heksE0uw///NX2SXop86++Ymb+k/FMkyGka8pg4y/pUlG+8uXyaU5b47R NuVYAUFEgEBj6Ve2jbZQP1qaTirSteIC0zdlVjyhHX3R3RcP8bYXQ++wlJswfpxjlv5d BHZsjwXIIBsFff5kosNUyESLkyYiqtPEdnF5/DNAFrfc1VV4HewQ1ZjA+Z/5HG7YQqeX CiKqVr11OMrmAyhLvpAMb+g4uOAPlxxKkcTG+6/MsOmmZEAixxe3mb8gJtuxJjW2QlMY VyCbchIQtv7AFxeBCXxmCygJd3BZLLG7XwiMAfx8cWmo7kUQn22FTkvmtM/ZUFPyxP29 VTaA== X-Gm-Message-State: AC+VfDyiWRdyF6NwNuFi0vuFAen6pgpHFq7vN/zftvyoYI7hWj0X9RWm 9FB1VNBA3EYhbonIeUfmUD/F1Ie2Ab0nzZNVqaCVczGtFcSBf/cVcOyfmvR4MZqpmxFhnY8BAPc m2GpQIpVVLIFyPojUCn+IXNXEFnn0AvZb0T2rT/G6Mknqvc6JwGMxyIWibdQU8iHNGcHKvASOOh JSSAfHZc28305VPI4= X-Google-Smtp-Source: ACHHUZ4HarBlrt7w5wC3w0gMuu62+7K9H3G8hOHQlJBusTnGINtatoDEV8k+cJjf2CL5U7wLG/4/dQ== X-Received: by 2002:a17:903:1108:b0:1b0:4883:2e03 with SMTP id n8-20020a170903110800b001b048832e03mr4028898plh.40.1685979733979; Mon, 05 Jun 2023 08:42:13 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:13 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Bagas Sanjaya , Jonathan Corbet , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Evan Green , Vincent Chen Subject: [PATCH -next v21 25/27] riscv: Add documentation for Vector Date: Mon, 5 Jun 2023 11:07:22 +0000 Message-Id: <20230605110724.21391-26-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230605_084215_130676_4A7C60C0 X-CRM114-Status: GOOD ( 27.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch add a brief documentation of the userspace interface in regard to the RISC-V Vector extension. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Vincent Chen Co-developed-by: Bagas Sanjaya Signed-off-by: Bagas Sanjaya --- Changelog v21: - add usage guideline into doc (Rémi) Changelog v20: - Drop bit-field repressentation and typos (Björn) - Fix document styling (Bagas) --- Documentation/riscv/index.rst | 1 + Documentation/riscv/vector.rst | 132 +++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/riscv/vector.rst diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 175a91db0200..95cf9c1e1da1 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -10,6 +10,7 @@ RISC-V architecture hwprobe patch-acceptance uabi + vector features diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst new file mode 100644 index 000000000000..48f189d79e41 --- /dev/null +++ b/Documentation/riscv/vector.rst @@ -0,0 +1,132 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================= +Vector Extension Support for RISC-V Linux +========================================= + +This document briefly outlines the interface provided to userspace by Linux in +order to support the use of the RISC-V Vector Extension. + +1. prctl() Interface +--------------------- + +Two new prctl() calls are added to allow programs to manage the enablement +status for the use of Vector in userspace. The intended usage guideline for +these interfaces is to give init systems a way to modify the availability of V +for processes running under its domain. Calling thess interfaces is not +recommended in libraries routines because libraries should not override policies +configured from the parant process. Also, users must noted that these interfaces +are not portable to non-Linux, nor non-RISC-V environments, so it is discourage +to use in a portable code. To get the availability of V in an ELF program, +please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the +auxiliary vector. + +* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg) + + Sets the Vector enablement status of the calling thread, where the control + argument consists of two 2-bit enablement statuses and a bit for inheritance + mode. Other threads of the calling process are unaffected. + + Enablement status is a tri-state value each occupying 2-bit of space in + the control argument: + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default + enablement status on execve(). The system-wide default setting can be + controlled via sysctl interface (see sysctl section below). + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the + thread. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector + instructions under such condition will trap and casuse the termination of the thread. + + arg: The control argument is a 5-bit value consisting of 3 parts, and + accessed by 3 masks respectively. + + The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK, + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT + represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the + enablement status of current thread, and the setting at bit[3:2] takes place + at next execve(). bit[4] defines the inheritance mode of the setting in + bit[3:2]. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the + Vector enablement status for the calling thread. The calling thread is + not able to turn off Vector once it has been enabled. The prctl() call + fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF + but the current enablement status is not off. Setting + PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back + the original enablement status. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the + Vector enablement setting for the calling thread at the next execve() + system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask, + then the enablement status will be decided by the system-wide + enablement status when execve() happen. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance + mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit + is set then the following execve() will not clear the setting in both + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT. + This setting persists across changes in the system-wide default value. + + Return value: + * 0 on success; + * EINVAL: Vector not supported, invalid enablement status for current or + next mask; + * EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector + was enabled for the calling thread. + + On success: + * A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place + immediately. The enablement status specified in + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or + all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is + set. + * Every successful call overwrites a previous setting for the calling + thread. + +* prctl(PR_RISCV_V_GET_CONTROL) + + Gets the same Vector enablement status for the calling thread. Setting for + next execve() call and the inheritance bit are all OR-ed together. + + Note that ELF programs are able to get the availability of V for itself by + reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the + auxiliary vector. + + Return value: + * a nonnegative value on success; + * EINVAL: Vector not supported. + +2. System runtime configuration (sysctl) +----------------------------------------- + +To mitigate the ABI impact of expansion of the signal stack, a +policy mechanism is provided to the administrators, distro maintainers, and +developers to control the default Vector enablement status for userspace +processes in form of sysctl knob: + +* /proc/sys/abi/riscv_v_default_allow + + Writing the text representation of 0 or 1 to this file sets the default + system enablement status for new starting userspace programs. Valid values + are: + + * 0: Do not allow Vector code to be executed as the default for new processes. + * 1: Allow Vector code to be executed as the default for new processes. + + Reading this file returns the current system default enablement status. + + At every execve() call, a new enablement status of the new process is set to + the system default, unless: + + * PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the + setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not + PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or, + + * The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not + PR_RISCV_V_VSTATE_CTRL_DEFAULT. + + Modifying the system default enablement status does not affect the enablement + status of any existing process of thread that do not make an execve() call.