[-next,v21,05/27] riscv: Clear vector regfile on bootup

Message ID	20230605110724.21391-6-andy.chiu@sifive.com (mailing list archive)
State	Accepted
Commit	6b533828726af4e3609aeb6e5f494e936f9a7cde
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Vincent Chen <vincent.chen@sifive.com>, Conor Dooley <conor.dooley@microchip.com>, Masahiro Yamada <masahiroy@kernel.org>, Guo Ren <guoren@kernel.org> Subject: [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Date: Mon, 5 Jun 2023 11:07:02 +0000 Message-Id: <20230605110724.21391-6-andy.chiu@sifive.com> In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: Add vector ISA support \| expand [-next,v21,00/27] riscv: Add vector ISA support [-next,v21,01/27] riscv: Rename __switch_to_aux() -> fpu [-next,v21,02/27] riscv: Extending cpufeature.c to detect V-extension [-next,v21,03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 [-next,v21,04/27] riscv: Add new csr defines related to vector extension [-next,v21,05/27] riscv: Clear vector regfile on bootup [-next,v21,06/27] riscv: Disable Vector Instructions for kernel itself [-next,v21,07/27] riscv: Introduce Vector enable/disable helpers [-next,v21,08/27] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v21,09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v21,10/27] riscv: Add task switch support for vector [-next,v21,11/27] riscv: Allocate user's vector context in the first-use trap [-next,v21,12/27] riscv: Add ptrace vector support [-next,v21,13/27] riscv: signal: check fp-reserved words unconditionally [-next,v21,14/27] riscv: signal: Add sigcontext save/restore for vector [-next,v21,15/27] riscv: signal: Report signal frame size to userspace via auxv [-next,v21,16/27] riscv: signal: validate altstack to reflect Vector [-next,v21,17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v21,18/27] riscv: kvm: Add V extension to KVM ISA [-next,v21,19/27] riscv: KVM: Add vector lazy save/restore support [-next,v21,20/27] riscv: hwcap: change ELF_HWCAP to a function [-next,v21,21/27] riscv: Add prctl controls for userspace vector management [-next,v21,22/27] riscv: Add sysctl to set the default vector rule for new processes [-next,v21,23/27] riscv: detect assembler support for .option arch [-next,v21,24/27] riscv: Enable Vector code to be built [-next,v21,25/27] riscv: Add documentation for Vector [-next,v21,26/27] selftests: Test RISC-V Vector prctl interface [-next,v21,27/27] selftests: add .gitignore file for RISC-V hwprobe

Message ID

20230605110724.21391-6-andy.chiu@sifive.com (mailing list archive)

State

Accepted

Commit

6b533828726af4e3609aeb6e5f494e936f9a7cde

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	anup@brainfault.org,
	atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org
Cc: vineetg@rivosinc.com,
	greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Vincent Chen <vincent.chen@sifive.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Guo Ren <guoren@kernel.org>
Subject: [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup
Date: Mon,  5 Jun 2023 11:07:02 +0000
Message-Id: <20230605110724.21391-6-andy.chiu@sifive.com>
In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com>
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Series

riscv: Add vector ISA support | expand

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Context	Check	Description
conchuod/cover_letter	success	Series has a cover letter
conchuod/tree_selection	success	Guessed tree name to be for-next at HEAD 90502d51ab90
conchuod/fixes_present	success	Fixes tag not required for -next series
conchuod/maintainers_pattern	success	MAINTAINERS pattern errors before the patch: 6 and now 6
conchuod/verify_signedoff	success	Signed-off-by tag matches author and committer
conchuod/kdoc	success	Errors and warnings before: 0 this patch: 0
conchuod/build_rv64_clang_allmodconfig	success	Errors and warnings before: 8 this patch: 8
conchuod/module_param	success	Was 0 now: 0
conchuod/build_rv64_gcc_allmodconfig	success	Errors and warnings before: 8 this patch: 8
conchuod/build_rv32_defconfig	success	Build OK
conchuod/dtb_warn_rv64	success	Errors and warnings before: 3 this patch: 3
conchuod/header_inline	success	No static functions without inline keyword in header files
conchuod/checkpatch	success	total: 0 errors, 0 warnings, 0 checks, 40 lines checked
conchuod/build_rv64_nommu_k210_defconfig	success	Build OK
conchuod/verify_fixes	success	No Fixes tag
conchuod/build_rv64_nommu_virt_defconfig	success	Build OK

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conchuod/cover_letter

success

Series has a cover letter

conchuod/tree_selection

success

Guessed tree name to be for-next at HEAD 90502d51ab90

conchuod/fixes_present

success

Fixes tag not required for -next series

conchuod/maintainers_pattern

success

MAINTAINERS pattern errors before the patch: 6 and now 6

conchuod/verify_signedoff

success

Signed-off-by tag matches author and committer

conchuod/kdoc

success

Errors and warnings before: 0 this patch: 0

conchuod/build_rv64_clang_allmodconfig

success

Errors and warnings before: 8 this patch: 8

conchuod/module_param

success

Was 0 now: 0

conchuod/build_rv64_gcc_allmodconfig

success

Errors and warnings before: 8 this patch: 8

conchuod/build_rv32_defconfig

success

Build OK

conchuod/dtb_warn_rv64

success

Errors and warnings before: 3 this patch: 3

conchuod/header_inline

success

No static functions without inline keyword in header files

conchuod/checkpatch

success

total: 0 errors, 0 warnings, 0 checks, 40 lines checked

conchuod/build_rv64_nommu_k210_defconfig

success

Build OK

conchuod/verify_fixes

success

No Fixes tag

conchuod/build_rv64_nommu_virt_defconfig

success

Build OK

Commit Message

Andy Chiu June 5, 2023, 11:07 a.m. UTC

From: Greentime Hu <greentime.hu@sifive.com>

clear vector registers on boot if kernel supports V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..3fd6a4bd9c3e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -392,7 +392,7 @@  ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	beqz	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done_fpu
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@  ENTRY(reset_regs)
 	fmv.s.x	f31, zero
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
+.Lreset_regs_done_fpu:
 #endif /* CONFIG_FPU */
-.Lreset_regs_done:
+
+#ifdef CONFIG_RISCV_ISA_V
+	csrr	t0, CSR_MISA
+	li	t1, COMPAT_HWCAP_ISA_V
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done_vector
+
+	/*
+	 * Clear vector registers and reset vcsr
+	 * VLMAX has a defined value, VLEN is a constant,
+	 * and this form of vsetvli is defined to set vl to VLMAX.
+	 */
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	csrs	CSR_VCSR, x0
+	vsetvli t1, x0, e8, m8, ta, ma
+	vmv.v.i v0, 0
+	vmv.v.i v8, 0
+	vmv.v.i v16, 0
+	vmv.v.i v24, 0
+	/* note that the caller must clear SR_VS */
+.Lreset_regs_done_vector:
+#endif /* CONFIG_RISCV_ISA_V */
 	ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */

[-next,v21,05/27] riscv: Clear vector regfile on bootup

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