| Message ID | 20230615-dubiously-parasail-79d34cefedce@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3c1b4758a9544cbaf38d052ad66a69618e920ceb |
| Headers | show |
| Series | dt-bindings: riscv: cpus: switch to unevaluatedProperties: false | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD d5e45e810e0e |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: Possible repeated word: 'that' |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, 15 Jun 2023 23:50:14 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > To permit validation of RISC-V cpu nodes, "additionalProperties: true" > needs to be swapped for "unevaluatedProperties: false". To facilitate > this in a way that passes dt_binding_check, a reference to the cpu > schema is required. > > Disallow the generic cache-op-block-size property that that drags in, > since the RISC-V CBO extensions do not require a common size, and have > individual properties. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 3d2934b15e80..e89a10d9c06b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -23,6 +23,9 @@ description: | two cores, each of which has two hyperthreads, could be described as having four harts. +allOf: + - $ref: /schemas/cpu.yaml# + properties: compatible: oneOf: @@ -98,6 +101,9 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + # RISC-V has multiple properties for cache op block sizes as the sizes + # differ between individual CBO extensions + cache-op-block-size: false # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false