| Message ID | 20230626-possible-poet-ae4afce0a525@wendy (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 488833ccdcac |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 2832 this patch: 2832 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 16511 this patch: 16511 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 20 this patch: 20 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 17 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Mon, Jun 26, 2023 at 12:19:43PM +0100, Conor Dooley wrote: > To facilitate adding single letter extensions to riscv_isa_ext, add > definitions for the extensions present in base_riscv_exts that do not > already have them. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/hwcap.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 36f46dfd2b87..a35bee219dd7 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -14,12 +14,17 @@ > #include <uapi/asm/hwcap.h> > > #define RISCV_ISA_EXT_a ('a' - 'a') > +#define RISCV_ISA_EXT_b ('b' - 'a') > #define RISCV_ISA_EXT_c ('c' - 'a') > #define RISCV_ISA_EXT_d ('d' - 'a') > #define RISCV_ISA_EXT_f ('f' - 'a') > #define RISCV_ISA_EXT_h ('h' - 'a') > #define RISCV_ISA_EXT_i ('i' - 'a') > +#define RISCV_ISA_EXT_j ('j' - 'a') > +#define RISCV_ISA_EXT_k ('k' - 'a') > #define RISCV_ISA_EXT_m ('m' - 'a') > +#define RISCV_ISA_EXT_p ('p' - 'a') > +#define RISCV_ISA_EXT_q ('q' - 'a') > #define RISCV_ISA_EXT_s ('s' - 'a') > #define RISCV_ISA_EXT_u ('u' - 'a') > #define RISCV_ISA_EXT_v ('v' - 'a') > -- > 2.40.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 36f46dfd2b87..a35bee219dd7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include <uapi/asm/hwcap.h> #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a')
To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+)