From patchwork Mon Jun 26 16:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= X-Patchwork-Id: 13293228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66124EB64D7 for ; Mon, 26 Jun 2023 16:58:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=thPKt8X7XIApWLd0pT3996Z0stECsH0ztdc0i3Lzxro=; b=f0MsUhwdFhwbZ4 XhnEtvkG8fVuRi04enjfHu/iTA6cX9k50BOxKmDlSFpqjW3EU7q3JPZt2R+HdtwPLGtpk/0PhYLFa dYKZKEAmaMwifJRrzzPOTgW1vcqHG4I0a3yoeroG8IZ3bJyXw9/J+7ip8EKLVvtRSLOM4qtGiOu7I z7Qj9r4wyM9xALY2wPAG2SJlvkEVy7CFnaciQ31tYsNF0GQXnmEXzzDv0R+p18TXWmsh+ZjAjRLSL +LtmT4udNYkEdHxmujD8rih6gsfOc/X0cc2ZqNJPRYtAKWZxKUe+SHmr/EA8wULDC0hQ+bD/3xs21 kTivi15WyMCfrZj5I7DQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qDpXH-00Ah1O-07; Mon, 26 Jun 2023 16:57:55 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qDpXE-00Ah0r-0l for linux-riscv@lists.infradead.org; Mon, 26 Jun 2023 16:57:53 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 702A360E93; Mon, 26 Jun 2023 16:57:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4411AC433C8; Mon, 26 Jun 2023 16:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687798670; bh=D7OOp/89DCaiYbQMxKU0tOSDhjvcdtKgZcq1oLiZYw8=; h=From:To:Cc:Subject:Date:From; b=mH7PKJVyDXTVMM0pvqVTZGZvdM1pTfAZhbM2tmvYqv21ZLuWCizd5/AqVqL2/EY6i sFJYZoHET3zvjjKjCXV06M/ruxB21ID8bExYeIy75+ZTY2Frv30nCMAqU4wq8jTBzs lfc49vv+jxFKL4s0cr9XO5JWA+PyLk9E9uurc6k5RZKuyt05qEq2SobHhk051/mB0q q7gwjoJ2UXZc6A6RpUXHPJoZpj3oLfgFqy/tECf4oOrk4zIrRqpWKISigmCKlc8LmI E2klUHvloTfAnOQHCbbUkdsjQP5yqf5gx0eGloy2PVLHQTjFc0sglpyFXTiaupH3Sj GGPSInHOFd0MQ== From: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , linux-kernel@vger.kernel.org, linux@rivosinc.com, Palmer Dabbelt , =?utf-8?q?R=C3=A9mi_Denis-Courmont?= , Darius Rad , Andy Chiu Subject: [PATCH v2] riscv: Discard vector state on syscalls Date: Mon, 26 Jun 2023 18:57:36 +0200 Message-Id: <20230626165736.65927-1-bjorn@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230626_095752_376829_0FA42F7D X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Björn Töpel The RISC-V vector specification states: Executing a system call causes all caller-saved vector registers (v0-v31, vl, vtype) and vstart to become unspecified. The vector registers are set to all 1s, vill is set (invalid), and the vector status is set to Initial. That way we can prevent userspace from accidentally relying on the stated save. Rémi pointed out [1] that writing to the registers might be superfluous, and setting vill is sufficient. Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] Suggested-by: Darius Rad Suggested-by: Palmer Dabbelt Suggested-by: Rémi Denis-Courmont Signed-off-by: Björn Töpel --- v1->v2: Proper register restore for initial state (Andy) Set registers to 1s, and not 0s (Darius) --- arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- arch/riscv/kernel/traps.c | 2 ++ 2 files changed, 41 insertions(+), 3 deletions(-) base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 04c0b07bf6cd..93d702d9988c 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, } } +static inline void __riscv_v_vstate_discard(void) +{ + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); + + riscv_v_enable(); + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vmv.v.i v0, -1\n\t" + "vmv.v.i v8, -1\n\t" + "vmv.v.i v16, -1\n\t" + "vmv.v.i v24, -1\n\t" + "vsetvl %0, x0, %1\n\t" + ".option pop\n\t" + : "=&r" (vl) : "r" (vtype_inval) : "memory"); + riscv_v_disable(); +} + +static inline void riscv_v_vstate_discard(struct pt_regs *regs) +{ + if (!riscv_v_vstate_query(regs)) + return; + + __riscv_v_vstate_discard(); + riscv_v_vstate_on(regs); +} + static inline void riscv_v_vstate_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) != SR_VS_OFF) { - struct __riscv_v_ext_state *vstate = &task->thread.vstate; - + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + unsigned long status = regs->status & SR_VS; + + switch (status) { + case SR_VS_INITIAL: + __riscv_v_vstate_discard(); + break; + case SR_VS_CLEAN: + case SR_VS_DIRTY: __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); + break; } } @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) +#define riscv_v_vstate_discard(regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 5158961ea977..5ff63a784a6d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) regs->epc += 4; regs->orig_a0 = regs->a0; + riscv_v_vstate_discard(regs); + syscall = syscall_enter_from_user_mode(regs, syscall); if (syscall < NR_syscalls)