| Message ID | 20230710192413.2089085-1-evan@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3] RISC-V: Show accurate per-hart isa in /proc/cpuinfo | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
On Mon, Jul 10, 2023 at 12:24:13PM -0700, Evan Green wrote: > +"isa" vs "hart isa" lines in /proc/cpuinfo > +----------------------------------------- This underline is too short :/
On Mon, Jul 10, 2023 at 12:24:13PM -0700, Evan Green wrote: > In /proc/cpuinfo, most of the information we show for each processor is > specific to that hart: marchid, mvendorid, mimpid, processor, hart, > compatible, and the mmu size. But the ISA string gets filtered through a > lowest common denominator mask, so that if one CPU is missing an ISA > extension, no CPUs will show it. > > Now that we track the ISA extensions for each hart, let's report ISA > extension info accurately per-hart in /proc/cpuinfo. We cannot change > the "isa:" line, as usermode may be relying on that line to show only > the common set of extensions supported across all harts. Add a new "hart > isa" line instead, which reports the true set of extensions for that > hart. This matches what is returned in riscv_hwprobe() when querying a > given hart. > > Signed-off-by: Evan Green <evan@rivosinc.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > Changes in v3: > - Add some documentation (Conor) > > Changes in v2: > - Added new "hart isa" line rather than altering behavior of existing > "isa" line (Conor, Palmer) > > > I based this series on top of Conor's riscv-extensions-strings branch > from July 3rd, since otherwise this change gets hopelessly entangled > with that series. > > --- > Documentation/riscv/uabi.rst | 10 ++++++++++ > arch/riscv/kernel/cpu.c | 22 ++++++++++++++++++---- > 2 files changed, 28 insertions(+), 4 deletions(-) > > diff --git a/Documentation/riscv/uabi.rst b/Documentation/riscv/uabi.rst > index 8960fac42c40..4f462f5b168c 100644 > --- a/Documentation/riscv/uabi.rst > +++ b/Documentation/riscv/uabi.rst > @@ -42,6 +42,16 @@ An example string following the order is:: > > rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux > > +"isa" vs "hart isa" lines in /proc/cpuinfo > +----------------------------------------- > + > +The "isa" line in /proc/cpuinfo describes the lowest common denominator of > +RISC-V ISA extensions understood by the kernel and implemented on all harts. The > +"hart isa" line, in contrast, describes the set of extensions understood by the > +kernel on the particular hart in question, even if those extensions may not be Maybe ...understood by the kernel for the specific hart associated with the "hart isa" line, even if... That's much wordier than "in question", but "in question" didn't ring well with me. Anyway, just food for thought, feel free to ignore. Thanks, drew > +present on all harts in the system. The "hart isa" line is consistent with > +what's returned by __riscv_hwprobe() when querying for that specific CPU. > + > Misaligned accesses > ------------------- > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 1acf3679600d..6264b7b94945 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -197,9 +197,8 @@ arch_initcall(riscv_cpuinfo_init); > > #ifdef CONFIG_PROC_FS > > -static void print_isa(struct seq_file *f) > +static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) > { > - seq_puts(f, "isa\t\t: "); > > if (IS_ENABLED(CONFIG_32BIT)) > seq_write(f, "rv32", 4); > @@ -207,7 +206,7 @@ static void print_isa(struct seq_file *f) > seq_write(f, "rv64", 4); > > for (int i = 0; i < riscv_isa_ext_count; i++) { > - if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) > + if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) > continue; > > /* Only multi-letter extensions are split by underscores */ > @@ -271,7 +270,15 @@ static int c_show(struct seq_file *m, void *v) > > seq_printf(m, "processor\t: %lu\n", cpu_id); > seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); > - print_isa(m); > + > + /* > + * For historical raisins, the isa: line is limited to the lowest common > + * denominator of extensions supported across all harts. A true list of > + * extensions supported on this hart is printed later in the hart_isa: > + * line. > + */ > + seq_puts(m, "isa\t\t: "); > + print_isa(m, NULL); > print_mmu(m); > > if (acpi_disabled) { > @@ -287,6 +294,13 @@ static int c_show(struct seq_file *m, void *v) > seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > + > + /* > + * Print the ISA extensions specific to this hart, which may show > + * additional extensions not present across all harts. > + */ > + seq_puts(m, "hart isa\t: "); > + print_isa(m, hart_isa[cpu_id].isa); > seq_puts(m, "\n"); > > return 0; > -- > 2.34.1 >
diff --git a/Documentation/riscv/uabi.rst b/Documentation/riscv/uabi.rst index 8960fac42c40..4f462f5b168c 100644 --- a/Documentation/riscv/uabi.rst +++ b/Documentation/riscv/uabi.rst @@ -42,6 +42,16 @@ An example string following the order is:: rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux +"isa" vs "hart isa" lines in /proc/cpuinfo +----------------------------------------- + +The "isa" line in /proc/cpuinfo describes the lowest common denominator of +RISC-V ISA extensions understood by the kernel and implemented on all harts. The +"hart isa" line, in contrast, describes the set of extensions understood by the +kernel on the particular hart in question, even if those extensions may not be +present on all harts in the system. The "hart isa" line is consistent with +what's returned by __riscv_hwprobe() when querying for that specific CPU. + Misaligned accesses ------------------- diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1acf3679600d..6264b7b94945 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -197,9 +197,8 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -static void print_isa(struct seq_file *f) +static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) { - seq_puts(f, "isa\t\t: "); if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); @@ -207,7 +206,7 @@ static void print_isa(struct seq_file *f) seq_write(f, "rv64", 4); for (int i = 0; i < riscv_isa_ext_count; i++) { - if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id)) continue; /* Only multi-letter extensions are split by underscores */ @@ -271,7 +270,15 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - print_isa(m); + + /* + * For historical raisins, the isa: line is limited to the lowest common + * denominator of extensions supported across all harts. A true list of + * extensions supported on this hart is printed later in the hart_isa: + * line. + */ + seq_puts(m, "isa\t\t: "); + print_isa(m, NULL); print_mmu(m); if (acpi_disabled) { @@ -287,6 +294,13 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); + + /* + * Print the ISA extensions specific to this hart, which may show + * additional extensions not present across all harts. + */ + seq_puts(m, "hart isa\t: "); + print_isa(m, hart_isa[cpu_id].isa); seq_puts(m, "\n"); return 0;