From patchwork Thu Jul 13 12:11:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13311931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28511C001DC for ; Thu, 13 Jul 2023 12:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ORQaigtl0TBEq8q79VIMeNbdz8zXm8UtxHLcB3Dnf3E=; b=uuPs95XVwAyeal ZoP8zWdUl+n5hV+x4KALCjjmnjMZr/8rvrOH3Q/xgKOx4OKeFXgj+ZLtvaOzVLf3OvgHLb22pIypb SJH8CveFvRxnMm1+aAq7KwYfZ9Zw195TkDcd+4USMjY+j7W1UvWce1W0Oif/slkUUurYFQQA9AwuP jbys1q3XcsvwFKIx8Y+BY4K0Y23tv1Wc/hS6YKYRyN0gilTF9j8RgOIemDStNkoJwA6ItyoilZooI uMVGS7ZPpa8DtMSiFCMApj57lA2rBEAcwaNIW+fB/Q0HOmY5DyRJvay4yHuRCLSgEJB2GwdXoWrYw qqY7E2z4i11b2ajtCuVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qJvBn-003BmD-1Z; Thu, 13 Jul 2023 12:12:55 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qJvBj-003BkF-2P for linux-riscv@lists.infradead.org; Thu, 13 Jul 2023 12:12:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250371; x=1720786371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iX4IZpSAWY+g6Eclm4yuSgD33Zp/aAK9fRllLAahOzo=; b=sSM2J74UeCKfekpjHfevAz/LPq5hm0GQM4zbfVrEFQCs6+wrdiThuKPI KzyYfRnH7AY7e94TApOU+kEox/rUExS0RsyJAtcCEi568QO2FSBufopvN /6ozOoX/F0S3D372lyKQu9KAtJi+gLXtkygWevQ8Q7cIoPKBQcOsSSrdn q/xTtnLYJBf7shbUQjcjNZ+KzdkFOmCfihWfx/CSC/cm4hZ91K9ESyhcg E7uZUde73pb867oO35vYgQtMftUgAdUeK5Aw1dCwSX1CdjNd3A2u7fd+A sG9ZYmInZsCn3vJLIEPDL/USuvjew02b391NtXpGBpcAKO54+WHhJ5AyL g==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="222827187" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:51 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:47 -0700 From: Conor Dooley To: Subject: [PATCH v5 07/11] RISC-V: add single letter extensions to riscv_isa_ext Date: Thu, 13 Jul 2023 13:11:05 +0100 Message-ID: <20230713-despite-bright-de00ac888cc7@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3714; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=iX4IZpSAWY+g6Eclm4yuSgD33Zp/aAK9fRllLAahOzo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX16zCF3y6Nz8A05vaooTdy1M41comyLx367wW2B2gAxX u3d/RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACaym4eR4f42hua8S1w3ar19oyQEay 9ZeKY8ef5x5xqOyEWrD//4GcXwz/LHfZmMM3bV7Gtnd9363HhLWK1q9aPbvFVb9a/ueMIbxA4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230713_051252_081446_72CB33AD X-CRM114-Status: GOOD ( 15.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Albert Ou , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, conor@kernel.org, conor.dooley@microchip.com, Rob Herring , Evan Green , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Heiko Stuebner , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org So that riscv_fill_hwcap() can use riscv_isa_ext to probe for single letter extensions, add them to it. As a result, what gets spat out in /proc/cpuinfo will become borked, as single letter extensions will be printed as part of the base extensions and while printing from riscv_isa_arr. Take the opportunity to unify the printing of the isa string, using the new member of riscv_isa_ext_data in the process. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop the multi_letter member, in exchange for calling strnlen() in two places. --- arch/riscv/kernel/cpu.c | 37 ++++++++++------------------------ arch/riscv/kernel/cpufeature.c | 13 ++++++++++++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index aa17eeb0ec9a..4f1f12f34b63 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,41 +164,26 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -static void print_isa_ext(struct seq_file *f) -{ - for (int i = 0; i < riscv_isa_ext_count; i++) { - const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->id)) - continue; - - seq_printf(f, "_%s", edata->name); - } -} - -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - static void print_isa(struct seq_file *f) { - int i; - seq_puts(f, "isa\t\t: "); + if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); else seq_write(f, "rv64", 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + continue; + + /* Only multi-letter extensions are split by underscores */ + if (strnlen(riscv_isa_ext[i].name, 2) != 1) + seq_puts(f, "_"); + + seq_printf(f, "%s", riscv_isa_ext[i].name); } - print_isa_ext(f); + seq_puts(f, "\n"); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 859e3831fac1..d6009bd4c186 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -144,6 +144,19 @@ static bool riscv_isa_extension_check(int id) * New entries to this struct should follow the ordering rules described above. */ const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), + __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), + __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), + __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), + __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b), + __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k), + __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j), + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),