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Mon, 24 Jul 2023 18:00:50 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2cbf:9196:a906:e222]) by smtp.gmail.com with ESMTPSA id h18-20020a62b412000000b00682a75a50e3sm8576900pfn.17.2023.07.24.18.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 18:00:49 -0700 (PDT) From: Drew Fustini Date: Mon, 24 Jul 2023 17:59:18 -0700 Subject: [PATCH RFC 4/4] mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 MIME-Version: 1.0 Message-Id: <20230724-th1520-emmc-v1-4-cca1b2533da2@baylibre.com> References: <20230724-th1520-emmc-v1-0-cca1b2533da2@baylibre.com> In-Reply-To: <20230724-th1520-emmc-v1-0-cca1b2533da2@baylibre.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Adrian Hunter , Ulf Hansson Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Robert Nelson , Jason Kridner , Drew Fustini X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690246840; l=3367; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=WInr0KFI/7RNGf1vlxj94FbnpVdO/HALVPPXj1tclFA=; b=CBoelk9cIZQkR6tFrZ3ZtNCai9EU670gQqx42gBZSNRwfdFkWvgCd5AOai2jGe9yXUz2Wgg+S 2UO2u/9flbcAZY3uJy/ldFwYzG2mR59LbFDFIOO1M0zIiBQxWyaI9oW X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230724_180051_730968_93ED4D50 X-CRM114-Status: GOOD ( 18.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add basic support for the T-Head TH1520 SoC mmc controller. The new compatible "thead,th1520-dwcmshc" enables basic support by: - Enabling v4 mode to properly communicate with the mmc device - Setting quirk to disable ADMA - Setting flag to disable SDMA and force PIO mode - Turing .reset op into a no-op as the driver does not yet know how to configure the phy. Rely on the vendor u-boot to have configured the phy and do not reset the controller in Linux. Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci-of-dwcmshc.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index e68cd87998c8..8573aff25a81 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -337,6 +337,14 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + /* + * MMC controller and phy is configured by vendor u-boot so + * take the simplistic approach of not doing reset in Linux. + */ +} + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -355,6 +363,15 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { .adma_write_desc = dwcmshc_adma_write_desc, }; +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = th1520_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { .ops = &sdhci_dwcmshc_ops, .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, @@ -378,6 +395,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_BROKEN_ADMA, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { int err; @@ -434,6 +458,10 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv } static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + { + .compatible = "thead,th1520-dwcmshc", + .data = &sdhci_dwcmshc_th1520_pdata, + }, { .compatible = "rockchip,rk3588-dwcmshc", .data = &sdhci_dwcmshc_rk35xx_pdata, @@ -546,6 +574,20 @@ static int dwcmshc_probe(struct platform_device *pdev) sdhci_enable_v4_mode(host); #endif + if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { + /* + * The controller needs v4 mode enabled to properly + * communicate with the mmc device. + */ + sdhci_enable_v4_mode(host); + + /* + * Set flag so the SDHCI host core will disable DMA + * and use PIO mode. + */ + host->flags &= ~SDHCI_USE_SDMA; + } + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; err = sdhci_setup_host(host);