From patchwork Mon Jul 31 13:43:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13334689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6663C001DE for ; Mon, 31 Jul 2023 13:52:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f1RFBiQLkyRZMVMnIEYTyEsPmmIyv5+gReTOxNmx/04=; b=OgJ7UFF4XBdz0D unduzyop69HzLg05IFHqJn/L41tvm4G0Qb4dQG1vLkuHiKtylk45wQZdhaggKZJ6c0cNnSXoChyLS uzLNWlnp0m5ROvdQapEktp/yF7PXxKz/rEMLOsnJySec6tdWGCk3sR8RzjPNSb9Cc7Pf4/5W3VXFZ D8wWLGyobshpZBs9g9xaKqLLmXeyQ3mljy0m37JlgAWzbLuS/1948U7oAzGA3P1Aiw7n6SrZQ1mu2 J8vVnHiGXBgPGAdZw/4+WjRj7xbq4Y9x5xfJXZTeMsA2ECNZDh8QMAcHXfJFIip2RRNCm7WAv3vTD rchBjZgJ6uKpWmqhv1iw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQTJe-00FsBu-2s; Mon, 31 Jul 2023 13:52:06 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQTJ3-00Frj1-08; Mon, 31 Jul 2023 13:51:30 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 55B3361167; Mon, 31 Jul 2023 13:51:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EDF23C433C9; Mon, 31 Jul 2023 13:51:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690811487; bh=sadX6jRs7DdBAThhpdGK2D3phr2V3dLQCMXle4b8GlY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tZ0mtVgGDNTbsC0me9RZvJkswmBEIQcoj/AN5nwmGFwL1Y8OVrdc2b0XShKGL4r9s puDP7rOxTZrPVPIfRMkV6t+XD/3ogD4QHdFEf/0+CGcRu3JeYKhRYCCQ9hhmweu/S6 j0w3nftlbmHhm8F7JB13RqCkpZMbhMSeMRBcDZdlF7jTQquihSs0pgIub+k7zXKFT/ saYc3fjnQDqqEInpE3ff1lC+8+A4OA1bBdwl6OH2rwb4nxOr4ih/JRuMhp+DT+sRnA Y5X8Gb7948++cW+lGGs1Kelkv7tzQtKSmpcpAKHkzfT8l4Vr7Hop9eHqszsHMHVXU5 B+5rwOZlXPb7w== From: Mark Brown Date: Mon, 31 Jul 2023 14:43:15 +0100 Subject: [PATCH v3 06/36] arm64/gcs: Add manual encodings of GCS instructions MIME-Version: 1.0 Message-Id: <20230731-arm64-gcs-v3-6-cddf9f980d98@kernel.org> References: <20230731-arm64-gcs-v3-0-cddf9f980d98@kernel.org> In-Reply-To: <20230731-arm64-gcs-v3-0-cddf9f980d98@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-099c9 X-Developer-Signature: v=1; a=openpgp-sha256; l=2577; i=broonie@kernel.org; h=from:subject:message-id; bh=sadX6jRs7DdBAThhpdGK2D3phr2V3dLQCMXle4b8GlY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkx7wYrQknxcMFlI+zXyyFjVrqAyFbdP30d9e19GKh YDA9b4qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZMe8GAAKCRAk1otyXVSH0LvYB/ 9nNuc0hiQ3DUndmYc0z2CG75eRkYkiKY1KKjiuK2A7oJzFhcasbQTA8d5ibJFwyccDP2QfoM8UJ7V7 vD6AivBvRHidGh3LAm7IgfoNE6g9cETUZZBe40ToD20JqWUQ/WAwL8VFDACP+BVZo6TWO1zakWM68H WGAyRdbnJ3ZidPiOG6EvZAIQtZcc3wre4PaJp7rTf0prFPBugkXDfFB1Le6GyqvuqxLUUFzTKckoKJ YqEV27W3dqNVQrCZR9K4HxBUXgvQ/Ldli4mpEOtc7p7MMR7sDhTe98w/vKoKuatsLmIOCvSDEB5mP0 fniuGIluMtAs+bPRvccs8MqjY/P9pG X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230731_065129_178286_9B09DE78 X-CRM114-Status: GOOD ( 17.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define C callable functions for GCS instructions used by the kernel. In order to avoid ambitious toolchain requirements for GCS support these are manually encoded, this means we have fixed register numbers which will be a bit limiting for the compiler but none of these should be used in sufficiently fast paths for this to be a problem. Note that GCSSTTR is used to store to EL0. Signed-off-by: Mark Brown --- arch/arm64/include/asm/gcs.h | 51 ++++++++++++++++++++++++++++++++++++++++ arch/arm64/include/asm/uaccess.h | 22 +++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h new file mode 100644 index 000000000000..7c5e95218db6 --- /dev/null +++ b/arch/arm64/include/asm/gcs.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 ARM Ltd. + */ +#ifndef __ASM_GCS_H +#define __ASM_GCS_H + +#include +#include + +static inline void gcsb_dsync(void) +{ + asm volatile(".inst 0xd503227f" : : : "memory"); +} + +static inline void gcsstr(u64 *addr, u64 val) +{ + register u64 *_addr __asm__ ("x0") = addr; + register long _val __asm__ ("x1") = val; + + /* GCSSTTR x1, x0 */ + asm volatile( + ".inst 0xd91f1c01\n" + : + : "rZ" (_val), "r" (_addr) + : "memory"); +} + +static inline void gcsss1(u64 Xt) +{ + asm volatile ( + "sys #3, C7, C7, #2, %0\n" + : + : "rZ" (Xt) + : "memory"); +} + +static inline u64 gcsss2(void) +{ + u64 Xt; + + asm volatile( + "SYSL %0, #3, C7, C7, #3\n" + : "=r" (Xt) + : + : "memory"); + + return Xt; +} + +#endif diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 14be5000c5a0..22e10e79f56a 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -425,4 +425,26 @@ static inline size_t probe_subpage_writeable(const char __user *uaddr, #endif /* CONFIG_ARCH_HAS_SUBPAGE_FAULTS */ +#ifdef CONFIG_ARM64_GCS + +static inline int gcssttr(unsigned long __user *addr, unsigned long val) +{ + register unsigned long __user *_addr __asm__ ("x0") = addr; + register unsigned long _val __asm__ ("x1") = val; + int err = 0; + + /* GCSSTTR x1, x0 */ + asm volatile( + "1: .inst 0xd91f1c01\n" + "2: \n" + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) + : "+r" (err) + : "rZ" (_val), "r" (_addr) + : "memory"); + + return err; +} + +#endif /* CONFIG_ARM64_GCS */ + #endif /* __ASM_UACCESS_H */