| Message ID | 20230807-arm64-gcs-v4-17-68cfa37f9069@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64/gcs: Provide support for GCS in userspace | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
On Mon, Aug 07, 2023 at 11:00:22PM +0100, Mark Brown wrote: > @@ -510,6 +527,26 @@ static vm_fault_t __do_page_fault(struct mm_struct *mm, > */ > if (!(vma->vm_flags & vm_flags)) > return VM_FAULT_BADACCESS; > + > + if (vma->vm_flags & VM_SHADOW_STACK) { > + /* > + * Writes to a GCS must either be generated by a GCS > + * operation or be from EL1. > + */ > + if (is_write_abort(esr) && > + !(is_gcs_fault(esr) || is_el1_data_abort(esr))) > + return VM_FAULT_BADACCESS; Related to my PIE permissions comment: when do we have a valid EL1 data write abort that's not a GCS fault? Does a faulting GCSSTTR set the ESR_ELx_GCS bit? > + } else { > + /* > + * GCS faults should never happen for pages that are > + * not part of a GCS and the operation being attempted > + * can never succeed. > + */ > + if (is_gcs_fault(esr)) > + return VM_FAULT_BADACCESS; If one does a GCS push/store to a non-GCS page, do we get a GCS fault or something else? I couldn't figure out from the engineering spec. If the hardware doesn't generate such exceptions, we might as well remove this 'else' branch. But maybe it does generate a GCS-specific fault as you added a similar check in is_invalid_el0_gcs_access(). > @@ -595,6 +644,19 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > if (!vma) > goto lock_mmap; > > + /* > + * We get legitimate write faults for GCS pages from GCS > + * operations and from EL1 writes to EL0 pages but just plain What are the EL1 writes to the shadow stack? Would it not use copy_to_user_gcs()?
On Fri, Aug 11, 2023 at 04:09:33PM +0100, Catalin Marinas wrote: > On Mon, Aug 07, 2023 at 11:00:22PM +0100, Mark Brown wrote: > > + if (is_write_abort(esr) && > > + !(is_gcs_fault(esr) || is_el1_data_abort(esr))) > > + return VM_FAULT_BADACCESS; > Related to my PIE permissions comment: when do we have a valid EL1 data > write abort that's not a GCS fault? Does a faulting GCSSTTR set the > ESR_ELx_GCS bit? Yes, it should do. The GCS instructions have access descriptors created with CreateAccDescGCS() which results in the access being flagged as a GCS access. > > + } else { > > + /* > > + * GCS faults should never happen for pages that are > > + * not part of a GCS and the operation being attempted > > + * can never succeed. > > + */ > > + if (is_gcs_fault(esr)) > > + return VM_FAULT_BADACCESS; > If one does a GCS push/store to a non-GCS page, do we get a GCS fault or > something else? I couldn't figure out from the engineering spec. If the > hardware doesn't generate such exceptions, we might as well remove this > 'else' branch. But maybe it does generate a GCS-specific fault as you > added a similar check in is_invalid_el0_gcs_access(). Yes, see AddGCSRecord() and LoadCheckGCSRecord() - all GCS initiated accesses need to be AccDescGCS so appropriate permissions enforcement can happen and that's what causes the fault to be flagged as GCS. > > @@ -595,6 +644,19 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > > if (!vma) > > goto lock_mmap; > > > > + /* > > + * We get legitimate write faults for GCS pages from GCS > > + * operations and from EL1 writes to EL0 pages but just plain > What are the EL1 writes to the shadow stack? Would it not use > copy_to_user_gcs()? They should, yes - I'll reword the comment.
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 3fe516b32577..ec392207a475 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -494,13 +494,30 @@ static void do_bad_area(unsigned long far, unsigned long esr, } } +/* + * Note: not valid for EL1 DC IVAC, but we never use that such that it + * should fault. EL0 cannot issue DC IVAC (undef). + */ +static bool is_write_abort(unsigned long esr) +{ + return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); +} + +static bool is_gcs_fault(unsigned long esr) +{ + if (!esr_is_data_abort(esr)) + return false; + + return ESR_ELx_ISS2(esr) & ESR_ELx_GCS; +} + #define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000) #define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000) static vm_fault_t __do_page_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned int mm_flags, unsigned long vm_flags, - struct pt_regs *regs) + unsigned long esr, struct pt_regs *regs) { /* * Ok, we have a good vm_area for this memory access, so we can handle @@ -510,6 +527,26 @@ static vm_fault_t __do_page_fault(struct mm_struct *mm, */ if (!(vma->vm_flags & vm_flags)) return VM_FAULT_BADACCESS; + + if (vma->vm_flags & VM_SHADOW_STACK) { + /* + * Writes to a GCS must either be generated by a GCS + * operation or be from EL1. + */ + if (is_write_abort(esr) && + !(is_gcs_fault(esr) || is_el1_data_abort(esr))) + return VM_FAULT_BADACCESS; + } else { + /* + * GCS faults should never happen for pages that are + * not part of a GCS and the operation being attempted + * can never succeed. + */ + if (is_gcs_fault(esr)) + return VM_FAULT_BADACCESS; + } + + return handle_mm_fault(vma, addr, mm_flags, regs); } @@ -518,13 +555,18 @@ static bool is_el0_instruction_abort(unsigned long esr) return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; } -/* - * Note: not valid for EL1 DC IVAC, but we never use that such that it - * should fault. EL0 cannot issue DC IVAC (undef). - */ -static bool is_write_abort(unsigned long esr) +static bool is_invalid_el0_gcs_access(struct vm_area_struct *vma, u64 esr) { - return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); + if (!system_supports_gcs()) + return false; + if (likely(!(vma->vm_flags & VM_SHADOW_STACK))) { + if (is_gcs_fault(esr)) + return true; + return false; + } + if (is_gcs_fault(esr)) + return false; + return is_write_abort(esr); } static int __kprobes do_page_fault(unsigned long far, unsigned long esr, @@ -573,6 +615,13 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, /* If EPAN is absent then exec implies read */ if (!cpus_have_const_cap(ARM64_HAS_EPAN)) vm_flags |= VM_EXEC; + /* + * Upgrade read faults to write faults, GCS reads must + * occur on a page marked as GCS so we need to trigger + * copy on write always. + */ + if (is_gcs_fault(esr)) + mm_flags |= FAULT_FLAG_WRITE; } if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { @@ -595,6 +644,19 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, if (!vma) goto lock_mmap; + /* + * We get legitimate write faults for GCS pages from GCS + * operations and from EL1 writes to EL0 pages but just plain + * EL0 writes are invalid. Specifically check for this since + * as a result of upgrading read faults to write faults for + * CoW the mm core isn't able to distinguish these invalid + * writes. + */ + if (is_invalid_el0_gcs_access(vma, esr)) { + vma_end_read(vma); + goto lock_mmap; + } + if (!(vma->vm_flags & vm_flags)) { vma_end_read(vma); goto lock_mmap; @@ -624,7 +686,7 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, goto done; } - fault = __do_page_fault(mm, vma, addr, mm_flags, vm_flags, regs); + fault = __do_page_fault(mm, vma, addr, mm_flags, vm_flags, esr, regs); /* Quick path to respond to signals */ if (fault_signal_pending(fault, regs)) {
All GCS operations at EL0 must happen on a page which is marked as having UnprivGCS access, including read operations. If a GCS operation attempts to access a page without this then it will generate a data abort with the GCS bit set in ESR_EL1.ISS2. EL0 may validly generate such faults, for example due to copy on write which will cause the GCS data to be stored in a read only page with no GCS permissions until the actual copy happens. Since UnprivGCS allows both reads and writes to the GCS (though only through GCS operations) we need to ensure that the memory management subsystem handles GCS accesses as writes at all times. Do this by adding FAULT_FLAG_WRITE to any GCS page faults, adding handling to ensure that invalid cases are identfied as such early so the memory management core does not think they will succeed. The core cannot distinguish between VMAs which are generally writeable and VMAs which are only writeable through GCS operations. EL1 may validly write to EL0 GCS for management purposes (eg, while initialising with cap tokens). We also report any GCS faults in VMAs not marked as part of a GCS as access violations, causing a fault to be delivered to userspace if it attempts to do GCS operations outside a GCS. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/mm/fault.c | 78 +++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 70 insertions(+), 8 deletions(-)