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[34.242.166.189]) by smtp.gmail.com with ESMTPSA id e15-20020a5d594f000000b00317df42e91dsm13921794wri.4.2023.09.12.15.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 15:46:56 -0700 (PDT) From: Puranjay Mohan To: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Shubham Bansal , Russell King , "James E.J. Bottomley" , Helge Deller , "Naveen N. Rao" , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Luke Nelson , Xi Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Wang YanQing , bpf@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org Cc: puranjay12@gmail.com Subject: [PATCH bpf-next 1/6] bpf, riscv32: Always zero extend for LDX with B/W/H Date: Tue, 12 Sep 2023 22:46:49 +0000 Message-Id: <20230912224654.6556-2-puranjay12@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230912224654.6556-1-puranjay12@gmail.com> References: <20230912224654.6556-1-puranjay12@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230912_154700_712511_A1F0E348 X-CRM114-Status: GOOD ( 11.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The JITs should not depend on the verifier for zero extending the upper 32 bits of the destination register when loading a byte, half-word, or word. A following patch will make the verifier stop patching zext instructions after LDX. Signed-off-by: Puranjay Mohan --- arch/riscv/net/bpf_jit_comp32.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/riscv/net/bpf_jit_comp32.c b/arch/riscv/net/bpf_jit_comp32.c index 529a83b85c1c..8f8255519ba1 100644 --- a/arch/riscv/net/bpf_jit_comp32.c +++ b/arch/riscv/net/bpf_jit_comp32.c @@ -847,18 +847,15 @@ static int emit_load_r64(const s8 *dst, const s8 *src, s16 off, switch (size) { case BPF_B: emit(rv_lbu(lo(rd), 0, RV_REG_T0), ctx); - if (!ctx->prog->aux->verifier_zext) - emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); + emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); break; case BPF_H: emit(rv_lhu(lo(rd), 0, RV_REG_T0), ctx); - if (!ctx->prog->aux->verifier_zext) - emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); + emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); break; case BPF_W: emit(rv_lw(lo(rd), 0, RV_REG_T0), ctx); - if (!ctx->prog->aux->verifier_zext) - emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); + emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); break; case BPF_DW: emit(rv_lw(lo(rd), 0, RV_REG_T0), ctx);