From patchwork Thu Sep 21 09:57:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A1B0E70704 for ; Thu, 21 Sep 2023 09:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2FcqJdX4YUVHwg4yRhoWAOH1eENonL3sgAoDkQ6bi+o=; b=Svw/GXG4Vby75X HrzuKMVwWQnSZeN7D7H5+o0A+bvoTvqEfW8Cvp+iwNi9EGeu4ZSWc6LIHJNdU5ptnHRMn6LwYSW0c Ds8Uf0dg9tO3vHSvRA6qBmUsJQLfsGFPYQMfA9OEWT+Gtd7mZBgWhGLrJ08/fJLXVLH6wwkJRdGCZ hz0cPKDrHyAfr/M0u2Q7qUEok9JLhKpj1NrnzuRqzvjbkqhhmELqEPk6llwj+XawGDLj/yBTGqIVC hkb4aZBHtgNwoS3M/hsA0OjywJO4rFztQSnwngZ6ttbgelo+9D9FhAZttNAKn9RiqEKHLp9lVJuO6 Jn48zrttAhbcnT0OCJEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRN-005eFn-2T; Thu, 21 Sep 2023 09:57:45 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRL-005eDw-0i for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:57:44 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 7EE12CE21A3; Thu, 21 Sep 2023 09:57:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 916D8C32788; Thu, 21 Sep 2023 09:57:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290259; bh=lMMt1zmmA3htZJsT6gS1oR0F3cSls2IHWYuOXnBLGug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ikA6d6dNjT+Iq1tz2TnKS3FAfVmVrwiv73dmdfm4olzziWJKC7iRk+TIewA/zSXjI AY8rugbz10ZUmbCqvZK6xQOT3OlL4L3X+D8UizRglrjTGjbtP2IZUCEcekFEM4Eyx3 F6RWn6xDoTDJZ6fmiT2cSAUR041Bt8iP8XGo0oWwr8/DaXuv8dch4siBYux71d4lvt RA4gkQefwN4FchqhGKY02tpefOhd+ZFv7d1ZFphMNN0vxpuCttKe1/8j6H5SzrLuix 0FVfTF3BZzNZMqK+EZkwC6epkeNMeDv587wfG+wT10zqZiOciU4vLGPCuumJ1d+/Vj h9pFJcqsR3tBQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 2/6] riscv: dts: sifive: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:19 +0100 Message-ID: <20230921095723.26456-3-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025743_620642_9BBFC1CB X-CRM114-Status: UNSURE ( 8.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 24bba83bec77..a7bd703206b3 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -30,6 +30,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -53,6 +56,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -77,6 +83,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -101,6 +110,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -125,6 +137,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 5235fd1c9cb6..06f9c86a6664 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -31,6 +31,9 @@ cpu0: cpu@0 { next-level-cache = <&ccache>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -55,6 +58,9 @@ cpu1: cpu@1 { next-level-cache = <&ccache>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -79,6 +85,9 @@ cpu2: cpu@2 { next-level-cache = <&ccache>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -103,6 +112,9 @@ cpu3: cpu@3 { next-level-cache = <&ccache>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -127,6 +139,9 @@ cpu4: cpu@4 { next-level-cache = <&ccache>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>;