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[5.147.49.11]) by smtp.gmail.com with UTF8SMTPSA id sa21-20020a170906edb500b009add084a00csm4007325ejb.36.2023.09.23.08.26.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 23 Sep 2023 08:26:54 -0700 (PDT) From: Daniel Maslowski X-Google-Original-From: Daniel Maslowski To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Daniel Maslowski Subject: [PATCH] riscv: dts: starfive: Add VisionFive 2 PHY supplies Date: Sat, 23 Sep 2023 17:26:53 +0200 Message-Id: <20230923152653.3371216-1-cyrevolt@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230923_082658_492237_8EEEA3C5 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org I checked the schematics to see what power supplies are needed. This allows for using ethernet without other drivers enabled that would coincidentally enable the same power supply. ⚡ Signed-off-by: Daniel Maslowski --- .../boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts index d4ea4a2c0b9b..bc1ac12bc71b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -16,12 +16,14 @@ &gmac0 { starfive,tx-use-rgmii-clk; assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + phy-supply = <&vcc_3v3>; }; &gmac1 { starfive,tx-use-rgmii-clk; assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; + phy-supply = <&vcc_3v3>; }; &phy0 {